Author: Mallikarjuna Gouda Date: 2025-05-07T12:12:06-04:00 New Revision: 55a88cdf53948e7460d9c6892f6c481480faa021
URL: https://github.com/llvm/llvm-project/commit/55a88cdf53948e7460d9c6892f6c481480faa021 DIFF: https://github.com/llvm/llvm-project/commit/55a88cdf53948e7460d9c6892f6c481480faa021.diff LOG: [MIPS] Add FeatureMSA to i6400 and i6500 cores (#134985) - Enable 'FeatureMSA' for MIPS i6400 and i6500 cpu. - Enable -mmsa option if mcpu is set to either i6400 or i6500 - added clang driver test to validate msa feature - added llvm codegen test to validate msa instructions for cpu i6500 and i6400 MIPS i6400 and i6500 cores implements and enables MSA (MIPS SIMD ARCHITECTURE) by default. Added: clang/test/Driver/mips-cpus.c Modified: clang/lib/Driver/ToolChains/Arch/Mips.cpp llvm/lib/Target/Mips/Mips.td llvm/test/CodeGen/Mips/msa/arithmetic.ll Removed: ################################################################################ diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp b/clang/lib/Driver/ToolChains/Arch/Mips.cpp index 9c817f238524c..960ee7fd179e1 100644 --- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp +++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp @@ -255,6 +255,12 @@ void mips::getMIPSTargetFeatures(const Driver &D, const llvm::Triple &Triple, D.Diag(diag::err_drv_unsupported_noabicalls_pic); } + if (CPUName == "i6500" || CPUName == "i6400") { + // MIPS cpu i6400 and i6500 support MSA (Mips SIMD Architecture) + // by default. + Features.push_back("+msa"); + } + if (!UseAbiCalls) Features.push_back("+noabicalls"); else diff --git a/clang/test/Driver/mips-cpus.c b/clang/test/Driver/mips-cpus.c new file mode 100644 index 0000000000000..2e988e58f04fb --- /dev/null +++ b/clang/test/Driver/mips-cpus.c @@ -0,0 +1,9 @@ +// Check target CPUs are correctly passed. + +// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6400 | FileCheck -check-prefix=MCPU-I6400 %s +// MCPU-I6400: "-target-cpu" "i6400" +// MCPU-I6400: "-target-feature" "+msa" "-target-feature" "-noabicalls" + +// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6500 | FileCheck -check-prefix=MCPU-I6500 %s +// MCPU-I6500: "-target-cpu" "i6500" +// MCPU-I6500: "-target-feature" "+msa" "-target-feature" "-noabicalls" diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td index 99415bcdbc20b..b346ba95f5984 100644 --- a/llvm/lib/Target/Mips/Mips.td +++ b/llvm/lib/Target/Mips/Mips.td @@ -243,11 +243,11 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl", // same CPU architecture. def ImplI6400 : SubtargetFeature<"i6400", "ProcImpl", "MipsSubtarget::CPU::I6400", - "MIPS I6400 Processor", [FeatureMips64r6]>; + "MIPS I6400 Processor", [FeatureMips64r6, FeatureMSA]>; def ImplI6500 : SubtargetFeature<"i6500", "ProcImpl", "MipsSubtarget::CPU::I6500", - "MIPS I6500 Processor", [FeatureMips64r6]>; + "MIPS I6500 Processor", [FeatureMips64r6, FeatureMSA]>; class Proc<string Name, list<SubtargetFeature> Features> : ProcessorModel<Name, MipsGenericModel, Features>; diff --git a/llvm/test/CodeGen/Mips/msa/arithmetic.ll b/llvm/test/CodeGen/Mips/msa/arithmetic.ll index a262ce183d74e..ad0493b694d48 100644 --- a/llvm/test/CodeGen/Mips/msa/arithmetic.ll +++ b/llvm/test/CodeGen/Mips/msa/arithmetic.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=ALL,MIPS ; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=ALL,MIPSEL +; RUN: llc -mtriple=mips64 -mcpu=i6500 < %s | FileCheck %s --check-prefixes=ALL +; RUN: llc -mtriple=mips64 -mcpu=i6400 < %s | FileCheck %s --check-prefixes=ALL define void @add_v16i8(ptr %c, ptr %a, ptr %b) nounwind { ; ALL-LABEL: add_v16i8: _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
