llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: Jim Lin (tclin914) <details> <summary>Changes</summary> The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. This patch only supports assembler. Intrinsics support will be added in a later patch. --- Full diff: https://github.com/llvm/llvm-project/pull/138827.diff 10 Files Affected: - (modified) clang/test/Driver/print-supported-extensions-riscv.c (+1) - (modified) llvm/docs/RISCVUsage.rst (+3) - (modified) llvm/docs/ReleaseNotes.md (+1) - (modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (+2-1) - (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+8) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td (+34) - (modified) llvm/test/CodeGen/RISCV/attributes.ll (+4) - (modified) llvm/test/CodeGen/RISCV/features-info.ll (+1) - (added) llvm/test/MC/RISCV/xandesvpackfph-valid.s (+39) - (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+1) ``````````diff diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index b10850aadddc3..f1c5d45db84c4 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -157,6 +157,7 @@ // CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory Types) // CHECK-NEXT: svvptc 1.0 'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid) // CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension) +// CHECK-NEXT: xandesvpackfph 5.0 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension) // CHECK-NEXT: xcvalu 1.0 'XCValu' (CORE-V ALU Operations) // CHECK-NEXT: xcvbi 1.0 'XCVbi' (CORE-V Immediate Branching) // CHECK-NEXT: xcvbitmanip 1.0 'XCVbitmanip' (CORE-V Bit Manipulation) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index d0689b779f551..80dd82342a8a3 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -508,6 +508,9 @@ The current vendor extensions supported are: ``XAndesPerf`` LLVM implements `version 5.0.0 of the Andes Performance Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>` by Andes Technology. All instructions are prefixed with `nds.` as described in the specification. +``XAndesVPackFPH`` + LLVM implements `version 5.0.0 of the Andes Vector Packed FP16 Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification. + Experimental C Intrinsics ========================= diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 0ed1675533d03..ffe21c5cad2a2 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -181,6 +181,7 @@ Changes to the RISC-V Backend interrupt handlers without using inline assembly. * Adds assembler support for the Andes `XAndesperf` (Andes Performance extension). * `-mcpu=sifive-p870` was added. +* Adds assembler support for the Andes `XAndesvpackfph` (Andes Vector Packed FP16 extension). Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 8f1b790826b24..ee8aa376f467d 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -727,7 +727,8 @@ static constexpr FeatureBitset XTHeadGroup = { RISCV::FeatureVendorXTHeadMemPair, RISCV::FeatureVendorXTHeadSync, RISCV::FeatureVendorXTHeadVdot}; -static constexpr FeatureBitset XAndesGroup = {RISCV::FeatureVendorXAndesPerf}; +static constexpr FeatureBitset XAndesGroup = { + RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesVPackFPH}; static constexpr DecoderListEntry DecoderList32[]{ // Vendor Extensions diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 18d341aa5b5ca..43e41f02c3f7a 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1517,6 +1517,14 @@ def HasVendorXAndesPerf AssemblerPredicate<(all_of FeatureVendorXAndesPerf), "'XAndesPerf' (Andes Performance Extension)">; +def FeatureVendorXAndesVPackFPH + : RISCVExtension<5, 0, "Andes Vector Packed FP16 Extension", + [FeatureStdExtZvfhmin]>; +def HasVendorXAndesVPackFPH + : Predicate<"Subtarget->hasVendorXAndesVPackFPH()">, + AssemblerPredicate<(all_of FeatureVendorXAndesVPackFPH), + "'XAndesVPackFPH' (Andes Vector Packed FP16 Extension)">; + //===----------------------------------------------------------------------===// // LLVM specific features and extensions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td index 2ec768435259c..b10a364b04d9f 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td @@ -305,6 +305,30 @@ class NDSRVInstSDGP<bits<3> funct3, string opcodestr> let mayStore = 1; } +class NDSRVInstVFPMAD<bits<6> funct6, string opcodestr> + : RVInst<(outs VR:$vd), (ins VR:$vs2, FPR32:$rs1, VMaskOp:$vm), + opcodestr # "." # "vf", "$vd, $rs1, $vs2$vm", [], InstFormatR>, + SchedTernaryMC<"WriteVFMulAddF", "ReadVFMulAddV", "ReadVFMulAddF", + "ReadVFWMulAddV"> { + bits<5> vs2; + bits<5> rs1; + bits<5> vd; + bit vm; + + let Inst{31-26} = funct6; + let Inst{25} = vm; + let Inst{24-20} = vs2; + let Inst{19-15} = rs1; + let Inst{14-12} = 0b100; + let Inst{11-7} = vd; + let Inst{6-0} = OPC_CUSTOM_2.Value; + let hasSideEffects = 0; + let mayLoad = 0; + let mayStore = 0; + + let RVVConstraint = VMConstraint; +} + //===----------------------------------------------------------------------===// // XAndesPerf //===----------------------------------------------------------------------===// @@ -355,4 +379,14 @@ def NDS_LDGP : NDSRVInstLDGP<0b011, "nds.ldgp">; def NDS_SDGP : NDSRVInstSDGP<0b111, "nds.sdgp">; } // Predicates = [HasVendorXAndesPerf, IsRV64] + +//===----------------------------------------------------------------------===// +// XAndesVPackFPH +//===----------------------------------------------------------------------===// + +let Predicates = [HasVendorXAndesVPackFPH], + Uses = [FRM, VL, VTYPE], mayRaiseFPException = true in { +def NDS_VFPMADT_VF : NDSRVInstVFPMAD<0b000010, "nds.vfpmadt">; +def NDS_VFPMADB_VF : NDSRVInstVFPMAD<0b000011, "nds.vfpmadb">; +} } // DecoderNamespace = "XAndes" diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 49e05f9acb4b2..ba4cbf9b567db 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -104,6 +104,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisync %s -o - | FileCheck --check-prefix=RV32XQCISYNC %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisls %s -o - | FileCheck --check-prefix=RV32XQCISLS %s ; RUN: llc -mtriple=riscv32 -mattr=+xandesperf %s -o - | FileCheck --check-prefix=RV32XANDESPERF %s +; RUN: llc -mtriple=riscv32 -mattr=+xandesvpackfph %s -o - | FileCheck --check-prefix=RV32XANDESVPACKFPH %s ; RUN: llc -mtriple=riscv32 -mattr=+zaamo %s -o - | FileCheck --check-prefix=RV32ZAAMO %s ; RUN: llc -mtriple=riscv32 -mattr=+zalrsc %s -o - | FileCheck --check-prefix=RV32ZALRSC %s ; RUN: llc -mtriple=riscv32 -mattr=+zca %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCA %s @@ -254,6 +255,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+xtheadsync %s -o - | FileCheck --check-prefix=RV64XTHEADSYNC %s ; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADVDOT %s ; RUN: llc -mtriple=riscv64 -mattr=+xandesperf %s -o - | FileCheck --check-prefix=RV64XANDESPERF %s +; RUN: llc -mtriple=riscv64 -mattr=+xandesvpackfph %s -o - | FileCheck --check-prefix=RV64XANDESVPACKFPH %s ; RUN: llc -mtriple=riscv64 -mattr=+za64rs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZA64RS %s ; RUN: llc -mtriple=riscv64 -mattr=+za128rs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZA128RS %s ; RUN: llc -mtriple=riscv64 -mattr=+zama16b %s -o - | FileCheck --check-prefixes=CHECK,RV64ZAMA16B %s @@ -447,6 +449,7 @@ ; RV32XQCISYNC: attribute 5, "rv32i2p1_zca1p0_xqcisync0p2" ; RV32XQCISLS: .attribute 5, "rv32i2p1_xqcisls0p2" ; RV32XANDESPERF: .attribute 5, "rv32i2p1_xandesperf5p0" +; RV32XANDESVPACKFPH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0_xandesvpackfph5p0" ; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo1p0" ; RV32ZALRSC: .attribute 5, "rv32i2p1_zalrsc1p0" ; RV32ZCA: .attribute 5, "rv32i2p1_zca1p0" @@ -598,6 +601,7 @@ ; RV64XTHEADSYNC: .attribute 5, "rv64i2p1_xtheadsync1p0" ; RV64XTHEADVDOT: .attribute 5, "rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0" ; RV64XANDESPERF: .attribute 5, "rv64i2p1_xandesperf5p0" +; RV64XANDESVPACKFPH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0_xandesvpackfph5p0" ; RV64ZTSO: .attribute 5, "rv64i2p1_ztso1p0" ; RV64ZAAMO: .attribute 5, "rv64i2p1_zaamo1p0" ; RV64ZALRSC: .attribute 5, "rv64i2p1_zalrsc1p0" diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 5f322dc04fedb..cdbb6e6425189 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -171,6 +171,7 @@ ; CHECK-NEXT: ventana-veyron - Ventana Veyron-Series processors. ; CHECK-NEXT: vxrm-pipeline-flush - VXRM writes causes pipeline flush. ; CHECK-NEXT: xandesperf - 'XAndesPerf' (Andes Performance Extension). +; CHECK-NEXT: xandesvpackfph - 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension). ; CHECK-NEXT: xcvalu - 'XCValu' (CORE-V ALU Operations). ; CHECK-NEXT: xcvbi - 'XCVbi' (CORE-V Immediate Branching). ; CHECK-NEXT: xcvbitmanip - 'XCVbitmanip' (CORE-V Bit Manipulation). diff --git a/llvm/test/MC/RISCV/xandesvpackfph-valid.s b/llvm/test/MC/RISCV/xandesvpackfph-valid.s new file mode 100644 index 0000000000000..955e71386d40b --- /dev/null +++ b/llvm/test/MC/RISCV/xandesvpackfph-valid.s @@ -0,0 +1,39 @@ +# XAndesVPackFPH - Andes Vector Packed FP16 Extension +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xandesvpackfph -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xandesvpackfph < %s \ +# RUN: | llvm-objdump --mattr=+xandesvpackfph -M no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s +# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc %s -triple=riscv64 -mattr=+xandesvpackfph -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xandesvpackfph < %s \ +# RUN: | llvm-objdump --mattr=+xandesvpackfph -M no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +# CHECK-OBJ: nds.vfpmadt.vf v8, fa0, v10 +# CHECK-ASM: nds.vfpmadt.vf v8, fa0, v10 +# CHECK-ASM: encoding: [0x5b,0x44,0xa5,0x0a] +# CHECK-ERROR: instruction requires the following: 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension){{$}} +nds.vfpmadt.vf v8, fa0, v10 + +# CHECK-OBJ: nds.vfpmadt.vf v8, fa0, v10, v0.t +# CHECK-ASM: nds.vfpmadt.vf v8, fa0, v10, v0.t +# CHECK-ASM: encoding: [0x5b,0x44,0xa5,0x08] +# CHECK-ERROR: instruction requires the following: 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension){{$}} +nds.vfpmadt.vf v8, fa0, v10, v0.t + +# CHECK-OBJ: nds.vfpmadb.vf v8, fa0, v10 +# CHECK-ASM: nds.vfpmadb.vf v8, fa0, v10 +# CHECK-ASM: encoding: [0x5b,0x44,0xa5,0x0e] +# CHECK-ERROR: instruction requires the following: 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension){{$}} +nds.vfpmadb.vf v8, fa0, v10 + +# CHECK-OBJ: nds.vfpmadb.vf v8, fa0, v10, v0.t +# CHECK-ASM: nds.vfpmadb.vf v8, fa0, v10, v0.t +# CHECK-ASM: encoding: [0x5b,0x44,0xa5,0x0c] +# CHECK-ERROR: instruction requires the following: 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension){{$}} +nds.vfpmadb.vf v8, fa0, v10, v0.t diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index b8d33e81e6c90..33133d302f338 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1128,6 +1128,7 @@ R"(All available -march extensions for RISC-V svpbmt 1.0 svvptc 1.0 xandesperf 5.0 + xandesvpackfph 5.0 xcvalu 1.0 xcvbi 1.0 xcvbitmanip 1.0 `````````` </details> https://github.com/llvm/llvm-project/pull/138827 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
