Author: Min-Yih Hsu Date: 2025-04-29T14:19:51-07:00 New Revision: 74593f667823025580e046e56d48d7a9899b8956
URL: https://github.com/llvm/llvm-project/commit/74593f667823025580e046e56d48d7a9899b8956 DIFF: https://github.com/llvm/llvm-project/commit/74593f667823025580e046e56d48d7a9899b8956.diff LOG: [RISCV][NFC] Remove duplicate extensions from tt-ascalon-d8 CPU (#137865) Sscofpmf is already in RVA23S64 and Zicsr is in RVA20U64. I also added a check against Sscofpmf. NFC. Added: Modified: clang/test/Driver/riscv-cpus.c llvm/lib/Target/RISCV/RISCVProcessors.td Removed: ################################################################################ diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index bb3a9d38be673..6fa401203361e 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -251,6 +251,7 @@ // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl256b" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl32b" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl64b" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+sscofpmf" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svinval" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svnapot" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svpbmt" diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 1ad94228bcbaa..822c25a4e1130 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -480,11 +480,9 @@ def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8", !listconcat(RVA23S64Features, [FeatureStdExtSmaia, FeatureStdExtSsaia, - FeatureStdExtSscofpmf, FeatureStdExtSsstrict, FeatureStdExtZfbfmin, FeatureStdExtZfh, - FeatureStdExtZicsr, FeatureStdExtZvbc, FeatureStdExtZvfbfmin, FeatureStdExtZvfbfwma, _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
