https://github.com/jyli0116 created
https://github.com/llvm/llvm-project/pull/137330
Added FEAT_FPAC onto supported AArch64 CPUs which don't have it under the
processor description.
>From 99ad372e888bd90595b1505368601fb0714653d0 Mon Sep 17 00:00:00 2001
From: Yu Li <yu...@arm.com>
Date: Fri, 25 Apr 2025 12:55:44 +0000
Subject: [PATCH] [AArch64] Add FEAT_FPAC to all supported CPUs
---
clang/test/CodeGen/AArch64/targetattr.c | 2 +-
.../aarch64-cortex-a510.c | 1 +
.../aarch64-cortex-a520.c | 1 +
.../aarch64-cortex-a520ae.c | 1 +
.../aarch64-cortex-a710.c | 1 +
.../aarch64-cortex-a715.c | 1 +
.../aarch64-cortex-a720.c | 1 +
.../aarch64-cortex-a720ae.c | 1 +
.../aarch64-cortex-a725.c | 1 +
.../aarch64-cortex-r82.c | 1 +
.../aarch64-cortex-r82ae.c | 1 +
.../aarch64-cortex-x2.c | 1 +
.../aarch64-cortex-x3.c | 1 +
.../aarch64-cortex-x4.c | 1 +
.../aarch64-neoverse-512tvb.c | 1 +
.../aarch64-neoverse-n2.c | 1 +
.../aarch64-neoverse-n3.c | 1 +
.../aarch64-neoverse-v3.c | 1 +
.../aarch64-neoverse-v3ae.c | 1 +
.../Preprocessor/aarch64-target-features.c | 2 +-
llvm/lib/Target/AArch64/AArch64Processors.td | 36 +++++++++----------
21 files changed, 38 insertions(+), 20 deletions(-)
diff --git a/clang/test/CodeGen/AArch64/targetattr.c
b/clang/test/CodeGen/AArch64/targetattr.c
index cfe115bf97ed3..d76e8e2248195 100644
--- a/clang/test/CodeGen/AArch64/targetattr.c
+++ b/clang/test/CodeGen/AArch64/targetattr.c
@@ -204,7 +204,7 @@ void applem4() {}
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a"
}
// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a"
}
// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
}
-// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-cpu"="cortex-a710"
"target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve-bitperm,+sve2,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a"
}
+// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-cpu"="cortex-a710"
"target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fpac,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve-bitperm,+sve2,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a"
}
// CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR6]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-cpu"="generic" "target-features"="+ete,+fp-armv8,+neon,+trbe,+v8a" }
// CHECK: attributes #[[ATTR7]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"tune-cpu"="generic" }
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a510.c
b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a510.c
index 4cd80eecf0a81..71ae6aa46acdc 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a510.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a510.c
@@ -20,6 +20,7 @@
// CHECK-NEXT: FEAT_FHM
Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP
Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16
Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC
Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FRINTTS
Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an
integer (in FP format) forcing it to fit into a 32- or 64-bit int
// CHECK-NEXT: FEAT_FlagM
Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_FlagM2
Enable alternative NZCV format for floating point comparisons
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c
b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c
index 6ddd52a4a7089..5c5f9ba81b5b8 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c
@@ -23,6 +23,7 @@
// CHECK-NEXT: FEAT_FHM
Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP
Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16
Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC
Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FRINTTS
Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an
integer (in FP format) forcing it to fit into a 32- or 64-bit int
// CHECK-NEXT: FEAT_FlagM
Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_FlagM2
Enable alternative NZCV format for floating point comparisons
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c
b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c
index 35399a3c85c62..d68fc6e744a29 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c
@@ -23,6 +23,7 @@
// CHECK-NEXT: FEAT_FHM
Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP
Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16
Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC
Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FRINTTS
Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an
integer (in FP format) forcing it to fit into a 32- or 64-bit int
// CHECK-NEXT: FEAT_FlagM
Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_FlagM2
Enable alternative NZCV format for floating point comparisons
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a710.c
b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a710.c
index f4ba17195cdf6..69c9495f113b9 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a710.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a710.c
@@ -20,6 +20,7 @@
// CHECK-NEXT: FEAT_FHM
Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP
Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16
Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC
Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FRINTTS
Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an
integer (in FP format) forcing it to fit into a 32- or 64-bit int
// CHECK-NEXT: FEAT_FlagM
Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_FlagM2
Enable alternative NZCV format for floating point comparisons
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a715.c
b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a715.c
index 3d04509b033f6..cec23c342680c 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a715.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a715.c
@@ -20,6 +20,7 @@
// CHECK-NEXT: FEAT_FHM
Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP
Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16
Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC
Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FRINTTS
Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an
integer (in FP format) forcing it to fit into a 32- or 64-bit int
// CHECK-NEXT: FEAT_FlagM
Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_FlagM2
Enable alternative NZCV format for floating point comparisons
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720.c
b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720.c
index a80bc038440c1..b7f0ae500ee5e 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720.c
@@ -23,6 +23,7 @@
// CHECK-NEXT: FEAT_FHM
Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP
Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16
Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC
Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FRINTTS
Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an
integer (in FP format) forcing it to fit into a 32- or 64-bit int
// CHECK-NEXT: FEAT_FlagM
Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_FlagM2
Enable alternative NZCV format for floating point comparisons
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720ae.c
b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720ae.c
index b2d5178650a67..8f7139afeca67 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720ae.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720ae.c
@@ -23,6 +23,7 @@
// CHECK-NEXT: FEAT_FHM
Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP
Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16
Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC
Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FRINTTS
Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an
integer (in FP format) forcing it to fit into a 32- or 64-bit int
// CHECK-NEXT: FEAT_FlagM
Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_FlagM2
Enable alternative NZCV format for floating point comparisons
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a725.c
b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a725.c
index 5dbf9ce72aa00..7c5e7c3624f69 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a725.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a725.c
@@ -23,6 +23,7 @@
// CHECK-NEXT: FEAT_FHM
Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP
Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16
Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC
Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FRINTTS
Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an
integer (in FP format) forcing it to fit into a 32- or 64-bit int
// CHECK-NEXT: FEAT_FlagM
Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_FlagM2
Enable alternative NZCV format for floating point comparisons
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82.c
b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82.c
index 9875c6922d379..2e22349ec9b48 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82.c
@@ -15,6 +15,7 @@
// CHECK-NEXT: FEAT_FHM
Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP
Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16
Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC
Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FlagM
Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_JSCVT
Enable Armv8.3-A JavaScript FP conversion instructions
// CHECK-NEXT: FEAT_LRCPC
Enable support for RCPC extension
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82ae.c
b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82ae.c
index 2db44d7827aad..c97517dbc5acd 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82ae.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82ae.c
@@ -15,6 +15,7 @@
// CHECK-NEXT: FEAT_FHM
Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP
Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16
Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC
Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FlagM
Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_JSCVT
Enable Armv8.3-A JavaScript FP conversion instructions
// CHECK-NEXT: FEAT_LRCPC
Enable support for RCPC extension
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x2.c
b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x2.c
index c4067dcb400ba..d98962c5487e0 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x2.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x2.c
@@ -20,6 +20,7 @@
// CHECK-NEXT: FEAT_FHM
Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP
Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16
Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC
Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FRINTTS
Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an
integer (in FP format) forcing it to fit into a 32- or 64-bit int
// CHECK-NEXT: FEAT_FlagM
Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_FlagM2
Enable alternative NZCV format for floating point comparisons
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x3.c
b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x3.c
index 97c1405b94a40..3104fc88b4011 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x3.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x3.c
@@ -20,6 +20,7 @@
// CHECK-NEXT: FEAT_FHM
Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP
Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16
Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC
Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FRINTTS
Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an
integer (in FP format) forcing it to fit into a 32- or 64-bit int
// CHECK-NEXT: FEAT_FlagM
Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_FlagM2
Enable alternative NZCV format for floating point comparisons
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x4.c
b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x4.c
index 7ccab05ddab6a..09ed3f285481b 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x4.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x4.c
@@ -23,6 +23,7 @@
// CHECK-NEXT: FEAT_FHM
Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP
Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16
Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC
Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FRINTTS
Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an
integer (in FP format) forcing it to fit into a 32- or 64-bit int
// CHECK-NEXT: FEAT_FlagM
Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_FlagM2
Enable alternative NZCV format for floating point comparisons
diff --git
a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-512tvb.c
b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-512tvb.c
index 4f890a2e4b71f..55f6ef56b6bc7 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-512tvb.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-512tvb.c
@@ -18,6 +18,7 @@
// CHECK-NEXT: FEAT_FHM
Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP
Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16
Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC
Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FlagM
Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_I8MM
Enable Matrix Multiply Int8 Extension
// CHECK-NEXT: FEAT_JSCVT
Enable Armv8.3-A JavaScript FP conversion instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n2.c
b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n2.c
index 12a35b7340cf3..5ad29837db1bd 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n2.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n2.c
@@ -20,6 +20,7 @@
// CHECK-NEXT: FEAT_FHM
Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP
Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16
Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC
Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FRINTTS
Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an
integer (in FP format) forcing it to fit into a 32- or 64-bit int
// CHECK-NEXT: FEAT_FlagM
Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_FlagM2
Enable alternative NZCV format for floating point comparisons
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n3.c
b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n3.c
index 942788d399997..9819a8388f039 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n3.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n3.c
@@ -23,6 +23,7 @@
// CHECK-NEXT: FEAT_FHM
Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP
Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16
Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC
Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FRINTTS
Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an
integer (in FP format) forcing it to fit into a 32- or 64-bit int
// CHECK-NEXT: FEAT_FlagM
Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_FlagM2
Enable alternative NZCV format for floating point comparisons
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3.c
b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3.c
index 89aef5a47f72c..f400d5bc3596e 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3.c
@@ -24,6 +24,7 @@
// CHECK-NEXT: FEAT_FHM
Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP
Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16
Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC
Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FRINTTS
Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an
integer (in FP format) forcing it to fit into a 32- or 64-bit int
// CHECK-NEXT: FEAT_FlagM
Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_FlagM2
Enable alternative NZCV format for floating point comparisons
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3ae.c
b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3ae.c
index eda46de652f6f..f478323257ec2 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3ae.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3ae.c
@@ -24,6 +24,7 @@
// CHECK-NEXT: FEAT_FHM
Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP
Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16
Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC
Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FRINTTS
Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an
integer (in FP format) forcing it to fit into a 32- or 64-bit int
// CHECK-NEXT: FEAT_FlagM
Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_FlagM2
Enable alternative NZCV format for floating point comparisons
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index b10c55447d9af..3f801c4344940 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -353,7 +353,7 @@
// CHECK-MCPU-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature"
"+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature"
"+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon"
"-target-feature" "+sha2"
// CHECK-MCPU-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature"
"+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature"
"+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon"
"-target-feature" "+sha2"
// CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"
"-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc"
"-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature"
"+perfmon" "-target-feature" "+sha2"
-// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"
"-target-feature" "+v8r" "-target-feature" "+ccdp" "-target-feature" "+ccpp"
"-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature"
"+dotprod" "-target-feature" "+flagm" "-target-feature" "+fp-armv8"
"-target-feature" "+fp16fml" "-target-feature" "+fullfp16" "-target-feature"
"+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature"
"+pauth" "-target-feature" "+perfmon" "-target-feature" "+predres"
"-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm"
"-target-feature" "+sb" "-target-feature" "+ssbs"
+// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"
"-target-feature" "+v8r" "-target-feature" "+ccdp" "-target-feature" "+ccpp"
"-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature"
"+dotprod" "-target-feature" "+flagm" "-target-feature" "+fp-armv8"
"-target-feature" "+fp16fml" "-target-feature" "+fpac" "-target-feature"
"+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse"
"-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature"
"+perfmon" "-target-feature" "+predres" "-target-feature" "+ras"
"-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sb"
"-target-feature" "+ssbs"
// CHECK-MCPU-M3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature"
"+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature"
"+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon"
"-target-feature" "+sha2"
// CHECK-MCPU-M4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature"
"+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature"
"+dotprod" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16"
"-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+perfmon"
"-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2"
// CHECK-MCPU-KRYO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature"
"+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature"
"+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon"
"-target-feature" "+sha2"
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td
b/llvm/lib/Target/AArch64/AArch64Processors.td
index c37dd025d80aa..c397e8d25b6ba 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -724,7 +724,7 @@ def ProcessorFeatures {
FeatureComplxNum, FeatureCRC, FeatureDotProd,
FeatureFPARMv8,FeatureFullFP16, FeatureJS,
FeatureLSE,
FeatureUseFixedOverScalableIfEqualCost,
- FeatureRAS, FeatureRCPC, FeatureRDM];
+ FeatureRAS, FeatureRCPC, FeatureRDM,
FeatureFPAC];
list<SubtargetFeature> A520 = [HasV9_2aOps, FeaturePerfMon, FeatureAM,
FeatureMTE, FeatureETE, FeatureSVEBitPerm,
FeatureFP16FML,
@@ -734,7 +734,7 @@ def ProcessorFeatures {
FeatureFPARMv8, FeatureFullFP16,
FeatureMatMulInt8, FeatureJS,
FeatureNEON, FeatureLSE, FeatureRAS,
FeatureRCPC, FeatureRDM,
FeatureUseFixedOverScalableIfEqualCost,
- FeatureDotProd];
+ FeatureDotProd, FeatureFPAC];
list<SubtargetFeature> A520AE = [HasV9_2aOps, FeaturePerfMon, FeatureAM,
FeatureMTE, FeatureETE, FeatureSVEBitPerm,
FeatureFP16FML,
@@ -743,7 +743,7 @@ def ProcessorFeatures {
FeatureSVE, FeatureSVE2, FeatureBF16,
FeatureComplxNum, FeatureCRC,
FeatureFPARMv8, FeatureFullFP16,
FeatureMatMulInt8, FeatureJS,
FeatureNEON, FeatureLSE, FeatureRAS,
FeatureRCPC, FeatureRDM,
- FeatureDotProd];
+ FeatureDotProd, FeatureFPAC];
list<SubtargetFeature> A65 = [HasV8_2aOps, FeatureSHA2, FeatureAES,
FeatureFPARMv8,
FeatureNEON, FeatureFullFP16, FeatureDotProd,
FeatureRCPC, FeatureSSBS, FeatureRAS,
@@ -773,7 +773,7 @@ def ProcessorFeatures {
FeatureCCIDX, FeatureSSBS,
FeatureETE, FeatureMTE, FeatureFP16FML,
FeatureSVEBitPerm, FeatureBF16,
FeatureMatMulInt8,
- FeaturePAuth, FeatureFlagM, FeatureSB,
FeatureSVE, FeatureSVE2,
+ FeaturePAuth, FeatureFlagM, FeatureSB,
FeatureSVE, FeatureSVE2, FeatureFPAC,
FeatureComplxNum, FeatureCRC, FeatureDotProd,
FeatureFPARMv8,
FeatureFullFP16, FeatureJS, FeatureLSE,
FeatureRAS, FeatureRCPC, FeatureRDM];
list<SubtargetFeature> A715 = [HasV9_0aOps, FeatureNEON, FeatureMTE,
@@ -785,7 +785,7 @@ def ProcessorFeatures {
FeatureSVE2, FeatureComplxNum, FeatureCRC,
FeatureDotProd, FeatureFPARMv8,
FeatureJS, FeatureLSE, FeatureRAS,
- FeatureRCPC, FeatureRDM];
+ FeatureRCPC, FeatureRDM, FeatureFPAC];
list<SubtargetFeature> A720 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
FeatureCCIDX,
FeatureTRBE, FeatureSVEBitPerm, FeatureETE,
@@ -794,7 +794,7 @@ def ProcessorFeatures {
FeatureSVE, FeatureSVE2, FeatureBF16,
FeatureComplxNum, FeatureCRC,
FeatureDotProd, FeatureFPARMv8,
FeatureFullFP16, FeatureMatMulInt8,
FeatureJS, FeatureLSE, FeatureNEON,
FeatureRAS,
- FeatureRCPC, FeatureRDM];
+ FeatureRCPC, FeatureRDM, FeatureFPAC];
list<SubtargetFeature> A720AE = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
FeatureCCIDX,
FeatureTRBE, FeatureSVEBitPerm, FeatureETE,
@@ -803,7 +803,7 @@ def ProcessorFeatures {
FeatureSVE, FeatureSVE2, FeatureBF16,
FeatureComplxNum, FeatureCRC,
FeatureDotProd, FeatureFPARMv8,
FeatureFullFP16, FeatureMatMulInt8,
FeatureJS, FeatureLSE, FeatureNEON,
FeatureRAS,
- FeatureRCPC, FeatureRDM];
+ FeatureRCPC, FeatureRDM, FeatureFPAC];
list<SubtargetFeature> A725 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
FeatureCCIDX,
FeatureETE, FeaturePerfMon, FeatureSPE,
@@ -812,21 +812,21 @@ def ProcessorFeatures {
FeatureSVE, FeatureSVE2, FeatureBF16,
FeatureComplxNum, FeatureCRC,
FeatureDotProd, FeatureFPARMv8,
FeatureFullFP16, FeatureMatMulInt8,
FeatureJS, FeatureLSE, FeatureNEON,
FeaturePAuth, FeatureRAS,
- FeatureRCPC, FeatureRDM];
+ FeatureRCPC, FeatureRDM, FeatureFPAC];
list<SubtargetFeature> R82 = [HasV8_0rOps, FeaturePerfMon, FeatureFullFP16,
FeatureFP16FML, FeatureSSBS, FeaturePredRes,
FeatureSB, FeatureRDM, FeatureDotProd,
FeatureComplxNum, FeatureJS,
FeatureCacheDeepPersist,
FeatureFlagM, FeatureCRC, FeatureLSE,
FeatureRAS, FeatureFPARMv8,
- FeatureNEON, FeaturePAuth, FeatureRCPC];
+ FeatureNEON, FeaturePAuth, FeatureRCPC,
FeatureFPAC];
list<SubtargetFeature> R82AE = [HasV8_0rOps, FeaturePerfMon, FeatureFullFP16,
FeatureFP16FML, FeatureSSBS, FeaturePredRes,
FeatureSB, FeatureRDM, FeatureDotProd,
FeatureComplxNum, FeatureJS,
FeatureCacheDeepPersist,
FeatureLSE, FeatureFlagM, FeatureCRC,
FeatureFPARMv8, FeatureNEON,
- FeaturePAuth, FeatureRAS, FeatureRCPC];
+ FeaturePAuth, FeatureRAS, FeatureRCPC,
FeatureFPAC];
list<SubtargetFeature> X1 = [HasV8_2aOps, FeatureSHA2, FeatureAES,
FeatureFPARMv8,
FeatureNEON, FeatureRCPC, FeaturePerfMon,
FeatureSPE, FeatureFullFP16, FeatureDotProd,
@@ -844,7 +844,7 @@ def ProcessorFeatures {
FeatureCCIDX,
FeaturePAuth, FeatureSSBS, FeatureSB,
FeatureSVE, FeatureSVE2, FeatureFlagM,
FeatureComplxNum, FeatureCRC, FeatureDotProd,
FeatureFPARMv8, FeatureFullFP16,
- FeatureJS, FeatureLSE, FeatureRAS,
FeatureRCPC, FeatureRDM];
+ FeatureJS, FeatureLSE, FeatureRAS,
FeatureRCPC, FeatureRDM, FeatureFPAC];
list<SubtargetFeature> X3 = [HasV9_0aOps, FeatureSVE, FeatureNEON,
FeaturePerfMon, FeatureETE, FeatureTRBE,
FeatureSPE, FeatureBF16, FeatureMatMulInt8,
@@ -853,7 +853,7 @@ def ProcessorFeatures {
FeatureCCIDX,
FeatureSB, FeaturePAuth, FeaturePredRes,
FeatureFlagM, FeatureSSBS,
FeatureSVE2, FeatureComplxNum, FeatureCRC,
FeatureFPARMv8, FeatureJS,
- FeatureLSE, FeatureRAS, FeatureRCPC,
FeatureRDM, FeatureDotProd];
+ FeatureLSE, FeatureRAS, FeatureRCPC,
FeatureRDM, FeatureDotProd, FeatureFPAC];
list<SubtargetFeature> X4 = [HasV9_2aOps,
FeaturePerfMon, FeatureETE, FeatureTRBE,
FeatureSPE, FeatureMTE, FeatureSVEBitPerm,
@@ -862,7 +862,7 @@ def ProcessorFeatures {
FeatureSB, FeatureSSBS, FeaturePAuth,
FeatureFlagM, FeaturePredRes,
FeatureSVE, FeatureSVE2, FeatureComplxNum,
FeatureCRC, FeatureDotProd,
FeatureFPARMv8, FeatureFullFP16,
FeatureMatMulInt8, FeatureJS, FeatureLSE,
- FeatureNEON, FeatureRAS, FeatureRCPC,
FeatureRDM, FeatureBF16];
+ FeatureNEON, FeatureRAS, FeatureRCPC,
FeatureRDM, FeatureBF16, FeatureFPAC];
list<SubtargetFeature> X925 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
FeatureCCIDX,
FeatureETE, FeaturePerfMon, FeatureSPE,
@@ -981,7 +981,7 @@ def ProcessorFeatures {
FeatureCCIDX,
FeatureDotProd, FeatureFullFP16,
FeatureSB, FeatureSSBS, FeatureSVE,
FeatureComplxNum, FeatureCRC,
FeatureFPARMv8, FeatureJS, FeatureLSE,
- FeatureNEON, FeaturePAuth, FeatureRAS,
FeatureRCPC, FeatureRDM];
+ FeatureNEON, FeaturePAuth, FeatureRAS,
FeatureRCPC, FeatureRDM, FeatureFPAC];
list<SubtargetFeature> NeoverseN3 = [HasV9_2aOps, FeatureETE, FeatureFP16FML,
FeatureFullFP16, FeatureMTE,
FeaturePerfMon,
FeatureRandGen, FeatureSPE,
FeatureSPE_EEF,
@@ -991,7 +991,7 @@ def ProcessorFeatures {
FeatureSVE, FeatureSVE2, FeatureBF16,
FeatureComplxNum,
FeatureCRC, FeatureDotProd,
FeatureFPARMv8, FeatureMatMulInt8,
FeatureJS, FeatureLSE, FeatureRAS,
FeatureRCPC, FeatureRDM,
- FeatureNEON];
+ FeatureNEON, FeatureFPAC];
list<SubtargetFeature> Neoverse512TVB = [HasV8_4aOps, FeatureBF16,
FeatureCacheDeepPersist,
FeatureSHA2, FeatureAES,
FeatureFPARMv8, FeatureFP16FML,
FeatureFullFP16, FeatureMatMulInt8,
FeatureNEON,
@@ -1000,7 +1000,7 @@ def ProcessorFeatures {
FeatureCCIDX,
FeatureSHA3, FeatureSM4,
FeatureDotProd, FeatureComplxNum,
FeatureCRC, FeatureJS, FeatureLSE,
FeaturePAuth, FeatureRAS,
- FeatureRCPC, FeatureRDM];
+ FeatureRCPC, FeatureRDM,
FeatureFPAC];
list<SubtargetFeature> NeoverseV1 = [HasV8_4aOps, FeatureBF16,
FeatureCacheDeepPersist,
FeatureSHA2, FeatureAES,
FeatureFPARMv8, FeatureFP16FML,
FeatureFullFP16, FeatureMatMulInt8,
FeatureNEON,
@@ -1026,7 +1026,7 @@ def ProcessorFeatures {
FeatureSSBS, FeatureSB, FeaturePredRes,
FeaturePAuth, FeatureFlagM,
FeatureSVE, FeatureSVE2, FeatureBF16,
FeatureComplxNum, FeatureCRC,
FeatureDotProd, FeatureFPARMv8,
FeatureMatMulInt8, FeatureJS, FeatureLSE,
- FeatureNEON, FeatureRAS, FeatureRCPC,
FeatureRDM, FeatureRME];
+ FeatureNEON, FeatureRAS, FeatureRCPC,
FeatureRDM, FeatureRME, FeatureFPAC];
list<SubtargetFeature> NeoverseV3AE = [HasV9_2aOps, FeatureETE,
FeatureFP16FML,
FeatureFullFP16, FeatureLS64, FeatureMTE,
FeaturePerfMon, FeatureRandGen,
FeatureSPE,
@@ -1036,7 +1036,7 @@ def ProcessorFeatures {
FeatureSVE, FeatureSVE2, FeatureBF16,
FeatureComplxNum, FeatureCRC,
FeatureDotProd, FeatureFPARMv8,
FeatureMatMulInt8, FeatureJS,
FeatureLSE, FeatureNEON, FeatureRAS,
FeatureRCPC, FeatureRDM,
- FeatureRME];
+ FeatureRME, FeatureFPAC];
list<SubtargetFeature> Saphira = [HasV8_4aOps, FeatureSHA2, FeatureAES,
FeatureFPARMv8,
FeatureNEON, FeatureSPE,
FeaturePerfMon, FeatureCRC,
FeatureCCIDX,
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