https://github.com/ChunyuLiao created https://github.com/llvm/llvm-project/pull/136556
spec: https://github.com/riscvarchive/riscv-smcntrpmf >From 21d3c26b4ad2d4d21af7c6269845b4e3a7b30b73 Mon Sep 17 00:00:00 2001 From: Liao Chunyu <chu...@iscas.ac.cn> Date: Mon, 21 Apr 2025 04:18:56 -0400 Subject: [PATCH] Add smcntrpmf extension spec: https://github.com/riscvarchive/riscv-smcntrpmf --- .../Driver/print-supported-extensions-riscv.c | 1 + .../test/Preprocessor/riscv-target-features.c | 9 ++++ llvm/docs/RISCVUsage.rst | 1 + llvm/lib/Target/RISCV/RISCVFeatures.td | 2 + llvm/lib/Target/RISCV/RISCVSystemOperands.td | 8 ++++ llvm/test/CodeGen/RISCV/attributes.ll | 4 ++ llvm/test/CodeGen/RISCV/features-info.ll | 1 + llvm/test/MC/RISCV/attribute-arch.s | 3 ++ llvm/test/MC/RISCV/user-csr-names.s | 48 +++++++++++++++++++ .../TargetParser/RISCVISAInfoTest.cpp | 1 + 10 files changed, 78 insertions(+) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 39002d7b4780a..66894e8b01468 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -123,6 +123,7 @@ // CHECK-NEXT: shvstvecd 1.0 'Shvstvecd' (vstvec supports Direct mode) // CHECK-NEXT: smaia 1.0 'Smaia' (Advanced Interrupt Architecture Machine Level) // CHECK-NEXT: smcdeleg 1.0 'Smcdeleg' (Counter Delegation Machine Level) +// CHECK-NEXT: smcntrpmf 1.0 'Smcntrpmf' (Cycle and instret privilege mode mode filtering) // CHECK-NEXT: smcsrind 1.0 'Smcsrind' (Indirect CSR Access Machine Level) // CHECK-NEXT: smdbltrp 1.0 'Smdbltrp' (Double Trap Machine Level) // CHECK-NEXT: smepmp 1.0 'Smepmp' (Enhanced Physical Memory Protection) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 253e42419f453..b5d3fcee38113 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -29,6 +29,7 @@ // CHECK-NOT: __riscv_shvstvecd {{.*$}} // CHECK-NOT: __riscv_smaia {{.*$}} // CHECK-NOT: __riscv_smcdeleg {{.*$}} +// CHECK-NOT: __riscv_smcntrpmf {{.*$}} // CHECK-NOT: __riscv_smcsrind {{.*$}} // CHECK-NOT: __riscv_smdbltrp {{.*$}} // CHECK-NOT: __riscv_smepmp {{.*$}} @@ -1453,6 +1454,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SMCSRIND-EXT %s // CHECK-SMCSRIND-EXT: __riscv_smcsrind 1000000{{$}} +// RUN: %clang --target=riscv32 \ +// RUN: -march=rv32ismcntrpmf1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMCNTRPMF-EXT %s +// RUN: %clang --target=riscv64 \ +// RUN: -march=rv64ismcntrpmf1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMCNTRPMF-EXT %s +// CHECK-SMCNTRPMF-EXT: __riscv_smcntrpmf 1000000{{$}} + // RUN: %clang --target=riscv32 \ // RUN: -march=rv32isscsrind1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SSCSRIND-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 137b537f00ea0..1ebe7b57abd7d 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -128,6 +128,7 @@ on support follow. ``Shvstvecd`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) ``Smaia`` Supported ``Smcdeleg`` Supported + ``Smcntrpmf`` Supported ``Smcsrind`` Supported ``Smdbltrp`` Supported ``Smepmp`` Supported diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index f51fcf82077f4..899a7fe45c37f 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -183,6 +183,8 @@ def FeatureStdExtZilsd def HasStdExtZilsd : Predicate<"Subtarget->hasStdExtZilsd()">, AssemblerPredicate<(all_of FeatureStdExtZilsd), "'Zilsd' (Load/Store pair instructions)">; +def FeatureStdExtSmcntrpmf + : RISCVExtension<1, 0, "Cycle and instret privilege mode mode filtering">; // Multiply Extensions diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td index 23388c7575e86..e2e812d749061 100644 --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -482,6 +482,14 @@ def : SysReg<"sctrdepth", 0x15f>; def : SysReg<"vsctrctl", 0x24e>; def : SysReg<"mctrctl", 0x34e>; +//===----------------------------------------------- +// Cycle and Instret privilege mode filtering (Smcntrpmf) +//===----------------------------------------------- +def : SysReg<"mcyclecfg", 0x321>; +def : SysReg<"minstretcfg", 0x322>; +def : SysReg<"mcyclecfgh", 0x721>; +def : SysReg<"minstretcfgh", 0x722>; + //===----------------------------------------------- // Vendor CSRs //===----------------------------------------------- diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 4bb3eb81f3dfb..b0dc65839559a 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -147,6 +147,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+ssdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV32SSDBLTRP %s ; RUN: llc -mtriple=riscv32 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s ; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s +; RUN: llc -mtriple=riscv32 -mattr=+smcntrpmf %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCNTRPMF %s ; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s ; RUN: llc -mtriple=riscv32 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV32SMRNMI %s ; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s @@ -301,6 +302,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+ssdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV64SSDBLTRP %s ; RUN: llc -mtriple=riscv64 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s ; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s +; RUN: llc -mtriple=riscv64 -mattr=+smcntrpmf %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCNTRPMF %s ; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s ; RUN: llc -mtriple=riscv64 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV64SMRNMI %s ; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s @@ -485,6 +487,7 @@ ; RV32SSDBLTRP: .attribute 5, "rv32i2p1_ssdbltrp1p0" ; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0" ; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0" +; RV32SMCNTRPMF: .attribute 5, "rv32i2p1_smcntrpmf1p0" ; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0" ; RV32SMRNMI: .attribute 5, "rv32i2p1_smrnmi1p0" ; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0" @@ -636,6 +639,7 @@ ; RV64SSDBLTRP: .attribute 5, "rv64i2p1_ssdbltrp1p0" ; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0" ; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0" +; RV64SMCNTRPMF: .attribute 5, "rv64i2p1_smcntrpmf1p0" ; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0" ; RV64SMRNMI: .attribute 5, "rv64i2p1_smrnmi1p0" ; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0" diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index d377bda059d33..91f27d319b04f 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -129,6 +129,7 @@ ; CHECK-NEXT: sifive7 - SiFive 7-Series processors. ; CHECK-NEXT: smaia - 'Smaia' (Advanced Interrupt Architecture Machine Level). ; CHECK-NEXT: smcdeleg - 'Smcdeleg' (Counter Delegation Machine Level). +; CHECK-NEXT: smcntrpmf - 'Smcntrpmf' (Cycle and instret privilege mode mode filtering). ; CHECK-NEXT: smcsrind - 'Smcsrind' (Indirect CSR Access Machine Level). ; CHECK-NEXT: smdbltrp - 'Smdbltrp' (Double Trap Machine Level). ; CHECK-NEXT: smepmp - 'Smepmp' (Enhanced Physical Memory Protection). diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 8edd6800a125f..16acd403eb9af 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -336,6 +336,9 @@ .attribute arch, "rv32i_smcdeleg1p0" # CHECK: attribute 5, "rv32i2p1_smcdeleg1p0" +.attribute arch, "rv32i_smcntrpmf1p0" +# CHECK: attribute 5, "rv32i2p1_smcntrpmf1p0" + .attribute arch, "rv32i_smepmp1p0" # CHECK: attribute 5, "rv32i2p1_smepmp1p0" diff --git a/llvm/test/MC/RISCV/user-csr-names.s b/llvm/test/MC/RISCV/user-csr-names.s index bc7363f0e67c8..f5cd193a1f5d1 100644 --- a/llvm/test/MC/RISCV/user-csr-names.s +++ b/llvm/test/MC/RISCV/user-csr-names.s @@ -480,3 +480,51 @@ csrrs t2, 0xC1E, zero csrrs t1, hpmcounter31, zero # uimm12 csrrs t2, 0xC1F, zero + +# mcyclecfg +# name +# CHECK-INST: csrrs t1, mcyclecfg, zero +# CHECK-ENC: encoding: [0x73,0x23,0x10,0x32] +# CHECK-INST-ALIAS: csrr t1, mcyclecfg +csrrs t1, mcyclecfg, zero +# uimm12 +# CHECK-INST: csrrs t2, mcyclecfg, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x32] +# CHECK-INST-ALIAS: csrr t2, mcyclecfg +csrrs t2, 0x321, zero + +# minstretcfg +# name +# CHECK-INST: csrrs t1, minstretcfg, zero +# CHECK-ENC: encoding: [0x73,0x23,0x20,0x32] +# CHECK-INST-ALIAS: csrr t1, minstretcfg +csrrs t1, minstretcfg, zero +# uimm12 +# CHECK-INST: csrrs t2, minstretcfg, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x32] +# CHECK-INST-ALIAS: csrr t2, minstretcfg +csrrs t2, 0x322, zero + +# mcyclecfgh +# name +# CHECK-INST: csrrs t1, mcyclecfgh, zero +# CHECK-ENC: encoding: [0x73,0x23,0x10,0x72] +# CHECK-INST-ALIAS: csrr t1, mcyclecfgh +csrrs t1, mcyclecfgh, zero +# uimm12 +# CHECK-INST: csrrs t2, mcyclecfgh, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x72] +# CHECK-INST-ALIAS: csrr t2, mcyclecfgh +csrrs t2, 0x721, zero + +# minstretcfgh +# name +# CHECK-INST: csrrs t1, minstretcfgh, zero +# CHECK-ENC: encoding: [0x73,0x23,0x20,0x72] +# CHECK-INST-ALIAS: csrr t1, minstretcfgh +csrrs t1, minstretcfgh, zero +# uimm12 +# CHECK-INST: csrrs t2, minstretcfgh, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x72] +# CHECK-INST-ALIAS: csrr t2, minstretcfgh +csrrs t2, 0x722, zero diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index ff0a5e64ab3e1..b8c8d7a9e55ef 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1076,6 +1076,7 @@ R"(All available -march extensions for RISC-V shvstvecd 1.0 smaia 1.0 smcdeleg 1.0 + smcntrpmf 1.0 smcsrind 1.0 smdbltrp 1.0 smepmp 1.0 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
