llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-mc Author: Djordje Todorovic (djtodoro) <details> <summary>Changes</summary> The right name was used in riscv-toolchain-conventions docs. --- Full diff: https://github.com/llvm/llvm-project/pull/135647.diff 15 Files Affected: - (modified) clang/test/Driver/print-supported-extensions-riscv.c (+1-1) - (modified) llvm/docs/RISCVUsage.rst (+1-1) - (modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (+2-2) - (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+6-6) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td (+2-2) - (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+1-1) - (modified) llvm/lib/Target/RISCV/RISCVSubtarget.cpp (+1-1) - (modified) llvm/test/CodeGen/RISCV/features-info.ll (+1-1) - (modified) llvm/test/CodeGen/RISCV/select-and.ll (+1-1) - (modified) llvm/test/CodeGen/RISCV/select-bare.ll (+1-1) - (modified) llvm/test/CodeGen/RISCV/select-cc.ll (+1-1) - (modified) llvm/test/CodeGen/RISCV/select-or.ll (+1-1) - (modified) llvm/test/MC/RISCV/xmips-invalid.s (+2-2) - (modified) llvm/test/MC/RISCV/xmips-valid.s (+3-3) - (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+1-1) ``````````diff diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index d06cedac5b1eb..39002d7b4780a 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -161,7 +161,7 @@ // CHECK-NEXT: xcvmac 1.0 'XCVmac' (CORE-V Multiply-Accumulate) // CHECK-NEXT: xcvmem 1.0 'XCVmem' (CORE-V Post-incrementing Load & Store) // CHECK-NEXT: xcvsimd 1.0 'XCVsimd' (CORE-V SIMD ALU) -// CHECK-NEXT: xmipscmove 1.0 'XMIPSCMove' (MIPS conditional move instruction(s) (ccmov)) +// CHECK-NEXT: xmipscmov 1.0 'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov)) // CHECK-NEXT: xmipslsp 1.0 'XMIPSLSP' (MIPS optimization for hardware load-store bonding) // CHECK-NEXT: xsfcease 1.0 'XSfcease' (SiFive sf.cease Instruction) // CHECK-NEXT: xsfvcp 1.0 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index cda7e5fec8488..137b537f00ea0 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -491,7 +491,7 @@ The current vendor extensions supported are: ``experimental-Xqcisync`` LLVM implements `version 0.2 of the Qualcomm uC Sync Delay extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. -``Xmipscmove`` +``Xmipscmov`` LLVM implements conditional move for the `p8700 processor <https://mips.com/products/hardware/p8700/>` by MIPS. ``Xmipslsp`` diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 366291b53bebb..27809d96b647c 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -737,8 +737,8 @@ static constexpr DecoderListEntry DecoderList32[]{ {DecoderTableXSfsystem32, XSfSystemGroup, "SiFive system extensions"}, {DecoderTableXSfcease32, {RISCV::FeatureVendorXSfcease}, "SiFive sf.cease"}, {DecoderTableXmipslsp32, {RISCV::FeatureVendorXMIPSLSP}, "MIPS mips.lsp"}, - {DecoderTableXmipscmove32, - {RISCV::FeatureVendorXMIPSCMove}, + {DecoderTableXmipscmov32, + {RISCV::FeatureVendorXMIPSCMov}, "MIPS mips.ccmov"}, // Standard Extensions {DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"}, diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 21bcf343139c2..f51fcf82077f4 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1300,12 +1300,12 @@ def HasVendorXCVbi "'XCVbi' (CORE-V Immediate Branching)">; // MIPS Extensions -def FeatureVendorXMIPSCMove - : RISCVExtension<1, 0, "MIPS conditional move instruction(s) (ccmov)">; -def HasVendorXMIPSCMove - : Predicate<"Subtarget->hasVendorXMIPSCMove()">, - AssemblerPredicate<(all_of FeatureVendorXMIPSCMove), - "'Xmipscmove' ('mips.ccmov' instruction)">; +def FeatureVendorXMIPSCMov + : RISCVExtension<1, 0, "MIPS conditional move instruction (mips.ccmov)">; +def HasVendorXMIPSCMov + : Predicate<"Subtarget->hasVendorXMIPSCMov()">, + AssemblerPredicate<(all_of FeatureVendorXMIPSCMov), + "'Xmipscmov' ('mips.ccmov' instruction)">; def UseCCMovInsn : Predicate<"Subtarget->useCCMovInsn()">; def FeatureVendorXMIPSLSP : RISCVExtension<1, 0, "MIPS optimization for hardware load-store bonding">; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td index 9be424310d660..ff751994b89b9 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td @@ -107,8 +107,8 @@ class SWPFormat<dag outs, dag ins, string opcodestr, string argstr> // MIPS extensions //===----------------------------------------------------------------------===// -let Predicates = [HasVendorXMIPSCMove], hasSideEffects = 0, mayLoad = 0, mayStore = 0, - DecoderNamespace = "Xmipscmove" in { +let Predicates = [HasVendorXMIPSCMov], hasSideEffects = 0, mayLoad = 0, mayStore = 0, + DecoderNamespace = "Xmipscmov" in { def MIPS_CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, GPR:$rs3), "mips.ccmov", "$rd, $rs2, $rs1, $rs3">, diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 9d48adeec5e86..ece12c48b1cd9 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -119,7 +119,7 @@ def MIPS_P8700 : RISCVProcessorModel<"mips-p8700", FeatureStdExtZbb, FeatureStdExtZifencei, FeatureStdExtZicsr, - FeatureVendorXMIPSCMove, + FeatureVendorXMIPSCMov, FeatureVendorXMIPSLSP], [TuneMIPSP8700]>; diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp index 3c996c82fcec4..b3c313f2ed394 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp @@ -253,5 +253,5 @@ bool RISCVSubtarget::useLoadStorePairs() const { } bool RISCVSubtarget::useCCMovInsn() const { - return UseCCMovInsn && HasVendorXMIPSCMove; + return UseCCMovInsn && HasVendorXMIPSCMov; } diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 5d2f0881048bd..d377bda059d33 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -174,7 +174,7 @@ ; CHECK-NEXT: xcvmac - 'XCVmac' (CORE-V Multiply-Accumulate). ; CHECK-NEXT: xcvmem - 'XCVmem' (CORE-V Post-incrementing Load & Store). ; CHECK-NEXT: xcvsimd - 'XCVsimd' (CORE-V SIMD ALU). -; CHECK-NEXT: xmipscmove - 'XMIPSCMove' (MIPS conditional move instruction(s) (ccmov)). +; CHECK-NEXT: xmipscmov - 'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov)). ; CHECK-NEXT: xmipslsp - 'XMIPSLSP' (MIPS optimization for hardware load-store bonding). ; CHECK-NEXT: xsfcease - 'XSfcease' (SiFive sf.cease Instruction). ; CHECK-NEXT: xsfvcp - 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions). diff --git a/llvm/test/CodeGen/RISCV/select-and.ll b/llvm/test/CodeGen/RISCV/select-and.ll index f827e840f4a36..2c9d0a8b56425 100644 --- a/llvm/test/CodeGen/RISCV/select-and.ll +++ b/llvm/test/CodeGen/RISCV/select-and.ll @@ -3,7 +3,7 @@ ; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+xmipscmove -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I-CCMOV %s ;; There are a few different ways to lower (select (and A, B), X, Y). This test diff --git a/llvm/test/CodeGen/RISCV/select-bare.ll b/llvm/test/CodeGen/RISCV/select-bare.ll index c9e108a1ca9d0..fc8eaa480b116 100644 --- a/llvm/test/CodeGen/RISCV/select-bare.ll +++ b/llvm/test/CodeGen/RISCV/select-bare.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I -; RUN: llc -mtriple=riscv64 -mattr=+xmipscmove -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I-CCMOV %s define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind { diff --git a/llvm/test/CodeGen/RISCV/select-cc.ll b/llvm/test/CodeGen/RISCV/select-cc.ll index 1c2a0cf007d11..e69dc303d85dc 100644 --- a/llvm/test/CodeGen/RISCV/select-cc.ll +++ b/llvm/test/CodeGen/RISCV/select-cc.ll @@ -3,7 +3,7 @@ ; RUN: | FileCheck -check-prefixes=RV32I %s ; RUN: llc -mtriple=riscv64 -disable-block-placement -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+xmipscmove -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I-CCMOV %s define signext i32 @foo(i32 signext %a, ptr %b) nounwind { diff --git a/llvm/test/CodeGen/RISCV/select-or.ll b/llvm/test/CodeGen/RISCV/select-or.ll index 338c7c06c3ab8..091c8b1a11e71 100644 --- a/llvm/test/CodeGen/RISCV/select-or.ll +++ b/llvm/test/CodeGen/RISCV/select-or.ll @@ -3,7 +3,7 @@ ; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+xmipscmove -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I-CCMOV %s ;; There are a few different ways to lower (select (or A, B), X, Y). This test diff --git a/llvm/test/MC/RISCV/xmips-invalid.s b/llvm/test/MC/RISCV/xmips-invalid.s index a1c1fd0666e0a..b3834e7b3407f 100644 --- a/llvm/test/MC/RISCV/xmips-invalid.s +++ b/llvm/test/MC/RISCV/xmips-invalid.s @@ -1,5 +1,5 @@ # RUN: not llvm-mc -triple=riscv64 < %s 2>&1 | FileCheck %s -check-prefixes=CHECK-FEATURE -# RUN: not llvm-mc -triple=riscv64 -mattr=+xmipslsp,+xmipscmove < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -triple=riscv64 -mattr=+xmipslsp,+xmipscmov < %s 2>&1 | FileCheck %s mips.ccmov x0, x1, 0x10 # CHECK: error: invalid operand for instruction @@ -8,7 +8,7 @@ mips.ccmov x10 # CHECK: error: too few operands for instruction mips.ccmov s0, s1, s2, s3 -# CHECK-FEATURE: error: instruction requires the following: 'Xmipscmove' ('mips.ccmov' instruction) +# CHECK-FEATURE: error: instruction requires the following: 'Xmipscmov' ('mips.ccmov' instruction) mips.lwp x10, x11 # CHECK: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/xmips-valid.s b/llvm/test/MC/RISCV/xmips-valid.s index ba256a823f511..9f31e4fa2038c 100644 --- a/llvm/test/MC/RISCV/xmips-valid.s +++ b/llvm/test/MC/RISCV/xmips-valid.s @@ -1,7 +1,7 @@ -# RUN: llvm-mc %s -triple=riscv64 -mattr=+xmipslsp,+xmipscmove -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+xmipslsp,+xmipscmov -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xmipslsp,+xmipscmove < %s \ -# RUN: | llvm-objdump --mattr=+xmipslsp,+xmipscmove -M no-aliases -d - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xmipslsp,+xmipscmov < %s \ +# RUN: | llvm-objdump --mattr=+xmipslsp,+xmipscmov -M no-aliases -d - \ # RUN: | FileCheck -check-prefix=CHECK-DIS %s # CHECK-INST: mips.ccmov s0, s1, s2, s3 diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 2ec27ba9d91b7..ff0a5e64ab3e1 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1114,7 +1114,7 @@ R"(All available -march extensions for RISC-V xcvmac 1.0 xcvmem 1.0 xcvsimd 1.0 - xmipscmove 1.0 + xmipscmov 1.0 xmipslsp 1.0 xsfcease 1.0 xsfvcp 1.0 `````````` </details> https://github.com/llvm/llvm-project/pull/135647 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
