================ @@ -1,34 +1,117 @@ // RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -x hlsl -emit-llvm -disable-llvm-passes -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-DXIL +// FIXME: SPIR-V codegen of llvm.spv.resource.handlefrombinding and resource types is not yet implemented // RUN-DISABLED: %clang_cc1 -triple spirv-vulkan-library -x hlsl -emit-llvm -disable-llvm-passes -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-SPIRV -// NOTE: SPIRV codegen for resource types is not yet implemented +// NOTE: Itanium ABI for C++ requires Clang to generate 2 constructors types to support polymorphism: +// - C1 - Complete object constructor - constructs the complete object, including virtual base classes. +// - C2 - Base object constructor - creates the object itself and initializes data members and non-virtual base classes. +// The constructors are distinquished by C1/C2 designators in their mangled name. +// https://itanium-cxx-abi.github.io/cxx-abi/abi.html#mangling-special-ctor-dtor -ByteAddressBuffer Buffer0: register(t0); -RWByteAddressBuffer Buffer1: register(u1, space2); -RasterizerOrderedByteAddressBuffer Buffer2: register(u3, space4); +// Resource with explicit binding +ByteAddressBuffer Buf1: register(t1, space2); -// CHECK: "class.hlsl::ByteAddressBuffer" = type { target("dx.RawBuffer", i8, 0, 0) } -// CHECK: "class.hlsl::RWByteAddressBuffer" = type { target("dx.RawBuffer", i8, 1, 0) } -// CHECK: "class.hlsl::RasterizerOrderedByteAddressBuffer" = type { target("dx.RawBuffer", i8, 1, 1) } +// Resource with implicit binding +RWByteAddressBuffer Buf2; -// CHECK: @_ZL7Buffer0 = internal global %"class.hlsl::ByteAddressBuffer" poison, align 4 -// CHECK: @_ZL7Buffer1 = internal global %"class.hlsl::RWByteAddressBuffer" poison, align 4 -// CHECK: @_ZL7Buffer2 = internal global %"class.hlsl::RasterizerOrderedByteAddressBuffer" poison, align 4 +export void foo() { + // Local resource declaration + RasterizerOrderedByteAddressBuffer Buf3; +} -// CHECK; define internal void @_init_resource_Buffer0() -// CHECK-DXIL: [[H:%.*]] = call target("dx.RawBuffer", i8, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i8_0_0t(i32 0, i32 0, i32 1, i32 0, i1 false) -// CHECK-DXIL: store target("dx.RawBuffer", i8, 0, 0) [[H]], ptr @_ZL7Buffer0, align 4 +// CHECK: %"class.hlsl::ByteAddressBuffer" = type { target("dx.RawBuffer", i8, 0, 0) } +// CHECK: %"class.hlsl::RWByteAddressBuffer" = type { target("dx.RawBuffer", i8, 1, 0) } +// CHECK: %"class.hlsl::RasterizerOrderedByteAddressBuffer" = type { target("dx.RawBuffer", i8, 1, 1) } -// CHECK; define internal void @_init_resource_Buffer1() -// CHECK-DXIL: [[H:%.*]] = call target("dx.RawBuffer", i8, 1, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i8_1_0t(i32 2, i32 1, i32 1, i32 0, i1 false) -// CHECK-DXIL: store target("dx.RawBuffer", i8, 1, 0) [[H]], ptr @_ZL7Buffer1, align 4 +// CHECK: @_ZL4Buf1 = internal global %"class.hlsl::ByteAddressBuffer" poison, align 4 +// CHECK: @_ZL4Buf2 = internal global %"class.hlsl::RWByteAddressBuffer" poison, align 4 -// CHECK; define internal void @_init_resource_Buffer2() -// CHECK-DXIL: [[H:%.*]] = call target("dx.RawBuffer", i8, 1, 1) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i8_1_1t(i32 4, i32 3, i32 1, i32 0, i1 false) -// CHECK-DXIL: store target("dx.RawBuffer", i8, 1, 1) [[H]], ptr @_ZL7Buffer2, align 4 +// Buf1 initialization part 1 - global init function that calls ByteAddressBuffer C1 constructor with explicit binding +// CHECK: define internal void @__cxx_global_var_init() +// CHECK-NEXT: entry: +// CHECK-NEXT: call void @_ZN4hlsl17ByteAddressBufferC1Ejjij(ptr noundef nonnull align 4 dereferenceable(4) @_ZL4Buf1, ---------------- V-FEXrt wrote:
Can we rely on consistent name mangling? I've been encouraging the new folks to regex out the mangled bit but maybe that isn't necessary? https://github.com/llvm/llvm-project/pull/135120 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
