================
@@ -91,6 +91,137 @@ if.end: ; preds =
%if.else, %if.then
%3 = load i32, ptr %resp, align 4
ret i32 %3
}
+
+; CHECK: define i32 @flatten_switch(i32 %X)
+; CHECK-NOT: hlsl.controlflow.hint
+; CHECK: switch i32 %0, label %sw.epilog [
+; CHECK-NEXT: i32 0, label %sw.bb
+; CHECK-NEXT: i32 1, label %sw.bb1
+; CHECK-NEXT: i32 2, label %sw.bb2
+; CHECK-NEXT: ], !dx.controlflow.hints [[HINT_FLATTEN]]
+define i32 @flatten_switch(i32 %X) #0 {
+entry:
+ %X.addr = alloca i32, align 4
+ %resp = alloca i32, align 4
+ store i32 %X, ptr %X.addr, align 4
+ %0 = load i32, ptr %X.addr, align 4
+ switch i32 %0, label %sw.epilog [
+ i32 0, label %sw.bb
+ i32 1, label %sw.bb1
+ i32 2, label %sw.bb2
+ ], !hlsl.controlflow.hint !1
+
+sw.bb: ; preds = %entry
+ %1 = load i32, ptr %X.addr, align 4
+ %sub = sub nsw i32 0, %1
+ store i32 %sub, ptr %resp, align 4
+ br label %sw.epilog
+
+sw.bb1: ; preds = %entry
+ %2 = load i32, ptr %X.addr, align 4
+ %3 = load i32, ptr %X.addr, align 4
+ %add = add nsw i32 %2, %3
+ store i32 %add, ptr %resp, align 4
+ br label %sw.epilog
+
+sw.bb2: ; preds = %entry
+ %4 = load i32, ptr %X.addr, align 4
+ %5 = load i32, ptr %X.addr, align 4
+ %mul = mul nsw i32 %4, %5
+ store i32 %mul, ptr %resp, align 4
+ br label %sw.epilog
+
+sw.epilog: ; preds = %entry, %sw.bb2,
%sw.bb1, %sw.bb
+ %6 = load i32, ptr %resp, align 4
+ ret i32 %6
+}
+
+
+; CHECK: define i32 @branch_switch(i32 %X)
+; CHECK-NOT: hlsl.controlflow.hint
+; CHECK: switch i32 %0, label %sw.epilog [
+; CHECK-NEXT: i32 0, label %sw.bb
+; CHECK-NEXT: i32 1, label %sw.bb1
+; CHECK-NEXT: i32 2, label %sw.bb2
+; CHECK-NEXT: ], !dx.controlflow.hints [[HINT_BRANCH]]
----------------
spall wrote:
is HINT_BRANCH supposed to be a 0?
https://github.com/llvm/llvm-project/pull/131739
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