================
@@ -1067,7 +1067,8 @@ def ProcessorFeatures {
FeatureDotProd, FeatureFPARMv8,
FeatureMatMulInt8,
FeatureSSBS, FeatureCCIDX,
FeatureJS, FeatureLSE, FeatureRAS,
FeatureRCPC, FeatureRDM];
- list<SubtargetFeature> Grace = !listconcat(NeoverseV2, [FeatureSVE2SM4,
FeatureSVEAES, FeatureSVE2SHA3]);
+ list<SubtargetFeature> Grace = !listconcat(NeoverseV2, [FeatureSVE2SM4,
FeatureSVEAES, FeatureSVE2SHA3,
+ FeatureFPAC]);
----------------
sjoerdmeijer wrote:
Thanks for spotting this, I think you're right. I got confused with
"supported", thinking about this architecturally, but this is in the V2 TRM, so
all V2 cores implement this. I will move this to the V2.
https://github.com/llvm/llvm-project/pull/133054
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