Author: Gergely Futo Date: 2025-03-10T10:13:33+01:00 New Revision: 3acfef56b1c5f74edd6ea2111a440677ea2c6763
URL: https://github.com/llvm/llvm-project/commit/3acfef56b1c5f74edd6ea2111a440677ea2c6763 DIFF: https://github.com/llvm/llvm-project/commit/3acfef56b1c5f74edd6ea2111a440677ea2c6763.diff LOG: [libunwind][RISCV] Make asm statement volatile (#130286) Compiling with `O3`, the `early-machinelicm` pass hoisted the asm statement to a path that has been executed unconditionally during stack unwinding. On hardware without vector extension support, this resulted in reading a nonexistent register. Added: Modified: libunwind/src/Registers.hpp Removed: ################################################################################ diff --git a/libunwind/src/Registers.hpp b/libunwind/src/Registers.hpp index 452f46a0d56ea..2c3bfb7e8428a 100644 --- a/libunwind/src/Registers.hpp +++ b/libunwind/src/Registers.hpp @@ -4126,7 +4126,7 @@ inline reg_t Registers_riscv::getRegister(int regNum) const { return _registers[regNum]; if (regNum == UNW_RISCV_VLENB) { reg_t vlenb; - __asm__("csrr %0, 0xC22" : "=r"(vlenb)); + __asm__ volatile("csrr %0, 0xC22" : "=r"(vlenb)); return vlenb; } _LIBUNWIND_ABORT("unsupported riscv register"); _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
