llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Helena Kotas (hekota) <details> <summary>Changes</summary> Fixes #<!-- -->130191 --- Full diff: https://github.com/llvm/llvm-project/pull/130223.diff 2 Files Affected: - (modified) clang/lib/CodeGen/Targets/DirectX.cpp (+8-2) - (modified) clang/test/CodeGenHLSL/builtins/RWBuffer-elementtype.hlsl (+4-3) ``````````diff diff --git a/clang/lib/CodeGen/Targets/DirectX.cpp b/clang/lib/CodeGen/Targets/DirectX.cpp index 77091eb45f5cf..0556527e2fdd6 100644 --- a/clang/lib/CodeGen/Targets/DirectX.cpp +++ b/clang/lib/CodeGen/Targets/DirectX.cpp @@ -59,8 +59,14 @@ llvm::Type *DirectXTargetCodeGenInfo::getHLSLType( SmallVector<unsigned, 3> Ints = {/*IsWriteable*/ ResAttrs.ResourceClass == llvm::dxil::ResourceClass::UAV, /*IsROV*/ ResAttrs.IsROV}; - if (!ResAttrs.RawBuffer) - Ints.push_back(/*IsSigned*/ ContainedTy->isSignedIntegerType()); + if (!ResAttrs.RawBuffer) { + const clang::Type *ElemType = ContainedTy->getUnqualifiedDesugaredType(); + if (ElemType->isVectorType()) + ElemType = cast<clang::VectorType>(ElemType) + ->getElementType() + ->getUnqualifiedDesugaredType(); + Ints.push_back(/*IsSigned*/ ElemType->isSignedIntegerType()); + } return llvm::TargetExtType::get(Ctx, TypeName, {ElemType}, Ints); } diff --git a/clang/test/CodeGenHLSL/builtins/RWBuffer-elementtype.hlsl b/clang/test/CodeGenHLSL/builtins/RWBuffer-elementtype.hlsl index 11c77644a906d..0944ad59d5fb5 100644 --- a/clang/test/CodeGenHLSL/builtins/RWBuffer-elementtype.hlsl +++ b/clang/test/CodeGenHLSL/builtins/RWBuffer-elementtype.hlsl @@ -10,10 +10,11 @@ // DXIL: %"class.hlsl::RWBuffer.5" = type { target("dx.TypedBuffer", half, 1, 0, 0) } // DXIL: %"class.hlsl::RWBuffer.6" = type { target("dx.TypedBuffer", float, 1, 0, 0) } // DXIL: %"class.hlsl::RWBuffer.7" = type { target("dx.TypedBuffer", double, 1, 0, 0) } -// DXIL: %"class.hlsl::RWBuffer.8" = type { target("dx.TypedBuffer", <4 x i16>, 1, 0, 0) } +// DXIL: %"class.hlsl::RWBuffer.8" = type { target("dx.TypedBuffer", <4 x i16>, 1, 0, 1) } // DXIL: %"class.hlsl::RWBuffer.9" = type { target("dx.TypedBuffer", <3 x i32>, 1, 0, 0) } // DXIL: %"class.hlsl::RWBuffer.10" = type { target("dx.TypedBuffer", <2 x half>, 1, 0, 0) } // DXIL: %"class.hlsl::RWBuffer.11" = type { target("dx.TypedBuffer", <3 x float>, 1, 0, 0) } +// DXIL: %"class.hlsl::RWBuffer.12" = type { target("dx.TypedBuffer", <4 x i32>, 1, 0, 1) } // SPIRV: %"class.hlsl::RWBuffer" = type { target("spirv.Image", i16, 5, 2, 0, 0, 2, 0) } // SPIRV: %"class.hlsl::RWBuffer.0" = type { target("spirv.Image", i16, 5, 2, 0, 0, 2, 0) } @@ -28,8 +29,7 @@ // SPIRV: %"class.hlsl::RWBuffer.9" = type { target("spirv.Image", i32, 5, 2, 0, 0, 2, 0) } // SPIRV: %"class.hlsl::RWBuffer.10" = type { target("spirv.Image", half, 5, 2, 0, 0, 2, 0) } // SPIRV: %"class.hlsl::RWBuffer.11" = type { target("spirv.Image", float, 5, 2, 0, 0, 2, 0) } - - +// SPIRV: %"class.hlsl::RWBuffer.12" = type { target("spirv.Image", i32, 5, 2, 0, 0, 2, 0) } RWBuffer<int16_t> BufI16; RWBuffer<uint16_t> BufU16; @@ -44,6 +44,7 @@ RWBuffer< vector<int16_t, 4> > BufI16x4; RWBuffer< vector<uint, 3> > BufU32x3; RWBuffer<half2> BufF16x2; RWBuffer<float3> BufF32x3; +RWBuffer<int4> BufI32x4; // TODO: RWBuffer<snorm half> BufSNormF16; -> 11 // TODO: RWBuffer<unorm half> BufUNormF16; -> 12 // TODO: RWBuffer<snorm float> BufSNormF32; -> 13 `````````` </details> https://github.com/llvm/llvm-project/pull/130223 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
