https://github.com/liliumShade updated
https://github.com/llvm/llvm-project/pull/123193
>From 08f81150949fb97411d6cc6e58c2b9f293cc1bf5 Mon Sep 17 00:00:00 2001
From: Chyaka <lilium23...@gmail.com>
Date: Thu, 16 Jan 2025 19:02:54 +0800
Subject: [PATCH 1/2] [RISCV] Add processor definition for
XiangShan-KunMingHu-V2R2
Co-Authored-By: Shenglin Tang <tangsheng...@ict.ac.cn>
Co-Authored-By: Xu, Zefan <ceba_ro...@outlook.com>
Co-Authored-By: Tang Haojin <tanghao...@outlook.com>
---
clang/test/Driver/riscv-cpus.c | 47 +++++++++++++++++++
.../test/Misc/target-invalid-cpu-note/riscv.c | 2 +
llvm/docs/ReleaseNotes.md | 1 +
llvm/lib/Target/RISCV/RISCVProcessors.td | 31 ++++++++++++
4 files changed, 81 insertions(+)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index e97b6940662d9fe..b9b27eec61c6f31 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -31,6 +31,53 @@
// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature"
"+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
// MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-kunminghu |
FileCheck -check-prefix=MCPU-XIANGSHAN-KUNMINGHU %s
+// MCPU-XIANGSHAN-KUNMINGHU: "-nostdsysteminc" "-target-cpu"
"xiangshan-kunminghu"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+m"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+a"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+f"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+d"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+c"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+b"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+v"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zic64b"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbom"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbop"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicboz"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccif"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicclsm"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccrse"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicntr"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicond"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicsr"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zacas"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zfh"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zba"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbb"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbc"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkb"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkc"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkx"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbs"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zkn"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zks"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvfh"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvl128b"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smcsrind"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smdbltrp"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smmpm"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smnpm"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smrnmi"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smstateen"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sscsrind"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssdbltrp"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sspm"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssstrict"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "-zawrs"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "-ziccamoa"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "-zihintntl"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-abi" "lp64d"
+
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-x60 | FileCheck
-check-prefix=MCPU-SPACEMIT-X60 %s
// MCPU-SPACEMIT-X60: "-nostdsysteminc" "-target-cpu" "spacemit-x60"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+m"
diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c
b/clang/test/Misc/target-invalid-cpu-note/riscv.c
index fb54dcb5b3a93aa..e9ed7ff47647751 100644
--- a/clang/test/Misc/target-invalid-cpu-note/riscv.c
+++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c
@@ -45,6 +45,7 @@
// RISCV64-SAME: {{^}}, syntacore-scr7
// RISCV64-SAME: {{^}}, tt-ascalon-d8
// RISCV64-SAME: {{^}}, veyron-v1
+// RISCV64-SAME: {{^}}, xiangshan-kunminghu
// RISCV64-SAME: {{^}}, xiangshan-nanhu
// RISCV64-SAME: {{$}}
@@ -94,6 +95,7 @@
// TUNE-RISCV64-SAME: {{^}}, syntacore-scr7
// TUNE-RISCV64-SAME: {{^}}, tt-ascalon-d8
// TUNE-RISCV64-SAME: {{^}}, veyron-v1
+// TUNE-RISCV64-SAME: {{^}}, xiangshan-kunminghu
// TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu
// TUNE-RISCV64-SAME: {{^}}, generic
// TUNE-RISCV64-SAME: {{^}}, rocket
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 8f88b824f965aa4..4a191bfbe594c74 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -199,6 +199,7 @@ Changes to the RISC-V Backend
* `-mcpu=tt-ascalon-d8` was added.
* `-mcpu=mips-p8700` was added.
* `-mcpu=sifive-p550` was added.
+* `-mcpu=xiangshan-kunminghu` was added.
* The `Zacas` extension is no longer marked as experimental.
* Added Smdbltrp, Ssdbltrp extensions to -march.
* The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 6dfed7ddeb9f635..2a434f30722804d 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -553,6 +553,37 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+ NoSchedModel,
+
!listconcat(!listremove(RVA23S64Features,
+ [FeatureStdExtZiccamoa,
+ FeatureStdExtZihintntl,
+ FeatureStdExtZawrs]),
+ [FeatureStdExtZicsr,
+ FeatureStdExtZacas,
+ FeatureStdExtZbc,
+ FeatureStdExtZfh,
+ FeatureStdExtZkn,
+ FeatureStdExtZks,
+ FeatureStdExtZvfh,
+ FeatureStdExtSmaia,
+ FeatureStdExtSmcsrind,
+ FeatureStdExtSmdbltrp,
+ FeatureStdExtSmmpm,
+ FeatureStdExtSmnpm,
+ FeatureStdExtSmrnmi,
+ FeatureStdExtSmstateen,
+ FeatureStdExtSsaia,
+ FeatureStdExtSscsrind,
+ FeatureStdExtSsdbltrp,
+ FeatureStdExtSspm,
+ FeatureStdExtSsstrict,
+ FeatureStdExtZvl128b]),
+ [TuneNoDefaultUnroll,
+ TuneZExtHFusion,
+ TuneZExtWFusion,
+ TuneShiftedZExtWFusion]>;
+
def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
NoSchedModel,
!listconcat(RVA22S64Features,
>From cefdeb071706bfc6428e2a900948ce9834e6e69b Mon Sep 17 00:00:00 2001
From: Chyaka <lilium23...@gmail.com>
Date: Fri, 7 Feb 2025 11:12:24 +0800
Subject: [PATCH 2/2] Add "ziccamoa" "zihintntl" and "zawrs"
Xiangshan-Kunminghu now compatible with RVA23S64 specification
Co-Authored-By: Shenglin Tang <tangsheng...@ict.ac.cn>
Co-Authored-By: Xu, Zefan <ceba_ro...@outlook.com>
Co-Authored-By: Tang Haojin <tanghao...@outlook.com>
---
clang/test/Driver/riscv-cpus.c | 6 +++---
llvm/lib/Target/RISCV/RISCVProcessors.td | 5 +----
2 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index b9b27eec61c6f31..cd15d6a3e0b4765 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -44,13 +44,16 @@
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbom"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbop"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicboz"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccamoa"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccif"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicclsm"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccrse"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicntr"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicond"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicsr"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zihintntl"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zacas"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zawrs"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zfh"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zba"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbb"
@@ -73,9 +76,6 @@
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssdbltrp"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sspm"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssstrict"
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "-zawrs"
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "-ziccamoa"
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "-zihintntl"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-abi" "lp64d"
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-x60 | FileCheck
-check-prefix=MCPU-SPACEMIT-X60 %s
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 2a434f30722804d..0ef8e4da728d14f 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -555,10 +555,7 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
NoSchedModel,
-
!listconcat(!listremove(RVA23S64Features,
- [FeatureStdExtZiccamoa,
- FeatureStdExtZihintntl,
- FeatureStdExtZawrs]),
+ !listconcat(RVA23S64Features,
[FeatureStdExtZicsr,
FeatureStdExtZacas,
FeatureStdExtZbc,
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