llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v @llvm/pr-subscribers-clang Author: Pengcheng Wang (wangpc-pp) <details> <summary>Changes</summary> **NOTE: This is an early-access support only for evaluation, not going to be merged and may be changable during the process of fast-track proposal.** ---- This PR contains the MC/CodeGen support of ByteDance's proposed Zvabd (Vector Absolute Difference) extension. Support of these instructions are added: - Vector Single-Width Signed/Unsigned Integer Absolute Difference - Vector Widening Signed/Unsigned Integer Absolute Difference and Accumulate Doc: https://bytedance.larkoffice.com/docx/DqaLdNqNao8WgZxgUJkcqIVPn7g --- Patch is 31.66 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/124239.diff 14 Files Affected: - (modified) clang/test/Driver/print-supported-extensions-riscv.c (+1) - (modified) clang/test/Preprocessor/riscv-target-features.c (+9) - (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+6) - (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+13-4) - (modified) llvm/lib/Target/RISCV/RISCVISelLowering.h (+4) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+1) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoV.td (+6-5) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td (+5-5) - (added) llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td (+47) - (modified) llvm/test/CodeGen/RISCV/attributes.ll (+4) - (modified) llvm/test/CodeGen/RISCV/rvv/abd.ll (+132) - (added) llvm/test/MC/RISCV/rvv/zvabd-invalid.s (+18) - (added) llvm/test/MC/RISCV/rvv/zvabd.s (+105) - (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+1) ``````````diff diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index ae3a1c29df3976..6c9ee75390fa88 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -183,6 +183,7 @@ // CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad) // CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack) // CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions) +// CHECK-NEXT: zvabd 0.2 'Zvabd' (Vector Absolute Difference) // CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements) // CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography) // CHECK-NEXT: sdext 1.0 'Sdext' (External debugger) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index c2197711352757..2725c283f107d1 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -145,6 +145,7 @@ // CHECK-NOT: __riscv_zksh {{.*$}} // CHECK-NOT: __riscv_zkt {{.*$}} // CHECK-NOT: __riscv_zmmul {{.*$}} +// CHECK-NOT: __riscv_zvabd {{.*$}} // CHECK-NOT: __riscv_zvbb {{.*$}} // CHECK-NOT: __riscv_zvbc {{.*$}} // CHECK-NOT: __riscv_zve32f {{.*$}} @@ -1504,6 +1505,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s // CHECK-ZFA-EXT: __riscv_zfa 1000000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zve64x_zvabd0p2 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVABD-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zve64x_zvabd0p2 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVABD-EXT %s +// CHECK-ZVABD-EXT: __riscv_zvabd 2000{{$}} + // RUN: %clang --target=riscv32 \ // RUN: -march=rv32i_zve64x_zvbb1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVBB-EXT %s diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 4119dd77804f1a..0937f378ca3d14 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -646,6 +646,12 @@ def FeatureStdExtV [FeatureStdExtZvl128b, FeatureStdExtZve64d]>, RISCVExtensionBitmask<0, 21>; +def FeatureStdExtZvabd + : RISCVExperimentalExtension<0, 2, "Vector Absolute Difference">; +def HasStdExtZvabd : Predicate<"Subtarget->hasStdExtZvabd()">, + AssemblerPredicate<(all_of FeatureStdExtZvabd), + "'Zvabd' (Vector Absolute Difference)">; + def FeatureStdExtZvfbfmin : RISCVExtension<1, 0, "Vector BF16 Converts", [FeatureStdExtZve32f]>; def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">, diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 618fb28d3e9f9a..6261ebdaa59a06 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -29,6 +29,7 @@ #include "llvm/CodeGen/MachineJumpTableInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAGAddressAnalysis.h" +#include "llvm/CodeGen/TargetLowering.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" #include "llvm/CodeGen/ValueTypes.h" #include "llvm/IR/DiagnosticInfo.h" @@ -830,7 +831,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, VT, Legal); - setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Custom); + if (Subtarget.hasStdExtZvabd()) + setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Legal); + else + setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Custom); // Custom-lower extensions and truncations from/to mask types. setOperationAction({ISD::ANY_EXTEND, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND}, @@ -1272,7 +1276,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction( {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX, ISD::ABS}, VT, Custom); - setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Custom); + if (Subtarget.hasStdExtZvabd()) + setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Legal); + else + setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Custom); // vXi64 MULHS/MULHU requires the V extension instead of Zve64*. if (VT.getVectorElementType() != MVT::i64 || Subtarget.hasStdExtV()) @@ -6502,7 +6509,7 @@ static bool hasPassthruOp(unsigned Opcode) { Opcode <= RISCVISD::LAST_STRICTFP_OPCODE && "not a RISC-V target specific op"); static_assert( - RISCVISD::LAST_VL_VECTOR_OP - RISCVISD::FIRST_VL_VECTOR_OP == 127 && + RISCVISD::LAST_VL_VECTOR_OP - RISCVISD::FIRST_VL_VECTOR_OP == 129 && RISCVISD::LAST_STRICTFP_OPCODE - RISCVISD::FIRST_STRICTFP_OPCODE == 21 && "adding target specific op should update this function"); if (Opcode >= RISCVISD::ADD_VL && Opcode <= RISCVISD::VFMAX_VL) @@ -6526,7 +6533,7 @@ static bool hasMaskOp(unsigned Opcode) { Opcode <= RISCVISD::LAST_STRICTFP_OPCODE && "not a RISC-V target specific op"); static_assert( - RISCVISD::LAST_VL_VECTOR_OP - RISCVISD::FIRST_VL_VECTOR_OP == 127 && + RISCVISD::LAST_VL_VECTOR_OP - RISCVISD::FIRST_VL_VECTOR_OP == 129 && RISCVISD::LAST_STRICTFP_OPCODE - RISCVISD::FIRST_STRICTFP_OPCODE == 21 && "adding target specific op should update this function"); if (Opcode >= RISCVISD::TRUNCATE_VECTOR_VL && Opcode <= RISCVISD::SETCC_VL) @@ -21020,6 +21027,8 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const { NODE_NAME_CASE(VZEXT_VL) NODE_NAME_CASE(VCPOP_VL) NODE_NAME_CASE(VFIRST_VL) + NODE_NAME_CASE(ABDS_VL) + NODE_NAME_CASE(ABDU_VL) NODE_NAME_CASE(READ_CSR) NODE_NAME_CASE(WRITE_CSR) NODE_NAME_CASE(SWAP_CSR) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index 77605a3076a80a..ed2244be25eb74 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -282,6 +282,10 @@ enum NodeType : unsigned { UMIN_VL, UMAX_VL, + // Vector Absolute Difference. + ABDS_VL, + ABDU_VL, + BITREVERSE_VL, BSWAP_VL, CTLZ_VL, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index bb5bb6352c32a5..0e0a05e8fc03b1 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -2110,6 +2110,7 @@ include "RISCVInstrInfoZk.td" // Vector include "RISCVInstrInfoV.td" include "RISCVInstrInfoZvk.td" +include "RISCVInstrInfoZvabd.td" // Compressed include "RISCVInstrInfoC.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td index 24a881dc6810f8..0d06efe6a488af 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -575,15 +575,16 @@ multiclass VALU_IV_X<string opcodestr, bits<6> funct6> { SchedBinaryMC<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX">; } -multiclass VALU_IV_I<string opcodestr, bits<6> funct6> { - def I : VALUVI<funct6, opcodestr # ".vi">, - SchedUnaryMC<"WriteVIALUI", "ReadVIALUV">; +multiclass VALU_IV_I<string opcodestr, bits<6> funct6, Operand optype = simm5> { + def I : VALUVI<funct6, opcodestr#".vi", optype>, + SchedUnaryMC<"WriteVIALUI", "ReadVIALUV">; } -multiclass VALU_IV_V_X_I<string opcodestr, bits<6> funct6> +multiclass VALU_IV_V_X_I<string opcodestr, bits<6> funct6, + Operand optype = simm5> : VALU_IV_V<opcodestr, funct6>, VALU_IV_X<opcodestr, funct6>, - VALU_IV_I<opcodestr, funct6>; + VALU_IV_I<opcodestr, funct6, optype>; multiclass VALU_IV_V_X<string opcodestr, bits<6> funct6> : VALU_IV_V<opcodestr, funct6>, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index 268bfe70673a2a..4bf5ba1edea801 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -2850,11 +2850,11 @@ multiclass VPseudoVFRDIV_VF_RM { } } -multiclass VPseudoVALU_VV_VX { - foreach m = MxList in { - defm "" : VPseudoBinaryV_VV<m>, - SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", m.MX, - forcePassthruRead=true>; +multiclass VPseudoVALU_VV_VX<bit Commutable = 0> { + foreach m = MxList in { + defm "" : VPseudoBinaryV_VV<m, Commutable = Commutable>, + SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", m.MX, + forcePassthruRead = true>; defm "" : VPseudoBinaryV_VX<m>, SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", m.MX, forcePassthruRead=true>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td new file mode 100644 index 00000000000000..6adc28f89b456a --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td @@ -0,0 +1,47 @@ +//===-- RISCVInstrInfoZvabd.td - 'Zvabd' instructions ------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// This file describes the RISC-V instructions for 'Zvabd' (Vector Absolute +/// Difference). +/// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instruction Definitions +//===----------------------------------------------------------------------===// +let Predicates = [HasStdExtZvabd] in { + defm VABD_V : VAALU_MV_V_X<"vabd", 0b010001>; + defm VABDU_V : VAALU_MV_V_X<"vabdu", 0b010011>; + + let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { + defm VWABDACC_V : VALU_MV_V_X<"vwabdacc", 0b010101, "v">; + defm VWABDACCU_V : VALU_MV_V_X<"vwabdaccu", 0b010110, "v">; + } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV +} // Predicates = [HasStdExtZvabd] + +//===----------------------------------------------------------------------===// +// Pseudos +//===----------------------------------------------------------------------===// +let Predicates = [HasStdExtZvabd] in { + defm PseudoVABD : VPseudoVALU_VV_VX<Commutable = 1>; + defm PseudoVABDU : VPseudoVALU_VV_VX<Commutable = 1>; +} // Predicates = [HasStdExtZvabd] + +//===----------------------------------------------------------------------===// +// CodeGen Patterns +//===----------------------------------------------------------------------===// +def riscv_abds_vl + : SDNode<"RISCVISD::ABDS_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; +def riscv_abdu_vl + : SDNode<"RISCVISD::ABDU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; + +defm : VPatBinarySDNode_VV_VX<abds, "PseudoVABD">; +defm : VPatBinarySDNode_VV_VX<abdu, "PseudoVABDU">; + +defm : VPatBinaryVL_VV_VX<riscv_abds_vl, "PseudoVABD">; +defm : VPatBinaryVL_VV_VX<riscv_abdu_vl, "PseudoVABDU">; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index caed0bdfb04984..a36d8c16a318e0 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -121,6 +121,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV32ZVKT %s ; RUN: llc -mtriple=riscv32 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV32ZVFH %s +; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvabd %s -o - | FileCheck --check-prefix=RV32ZVABD %s ; RUN: llc -mtriple=riscv32 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s ; RUN: llc -mtriple=riscv32 -mattr=+zimop %s -o - | FileCheck --check-prefix=RV32ZIMOP %s ; RUN: llc -mtriple=riscv32 -mattr=+zcmop %s -o - | FileCheck --check-prefix=RV32ZCMOP %s @@ -270,6 +271,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s ; RUN: llc -mtriple=riscv64 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV64ZVFH %s +; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvabd %s -o - | FileCheck --check-prefix=RV64ZVABD %s ; RUN: llc -mtriple=riscv64 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s ; RUN: llc -mtriple=riscv64 -mattr=+zimop %s -o - | FileCheck --check-prefix=RV64ZIMOP %s ; RUN: llc -mtriple=riscv64 -mattr=+zcmop %s -o - | FileCheck --check-prefix=RV64ZCMOP %s @@ -437,6 +439,7 @@ ; RV32ZVKSH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh1p0_zvl32b1p0" ; RV32ZVKT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0" ; RV32ZVFH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0" +; RV32ZVABD: .attribute 5, "rv32i2p1_zicsr2p0_zvabd0p2_zve32x1p0_zvl32b1p0" ; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0" ; RV32ZIMOP: .attribute 5, "rv32i2p1_zimop1p0" ; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop1p0" @@ -584,6 +587,7 @@ ; RV64ZVKSH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksh1p0_zvl32b1p0" ; RV64ZVKT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0" ; RV64ZVFH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0" +; RV64ZVABD: .attribute 5, "rv64i2p1_zicsr2p0_zvabd0p2_zve32x1p0_zvl32b1p0" ; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0" ; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop1p0" ; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop1p0" diff --git a/llvm/test/CodeGen/RISCV/rvv/abd.ll b/llvm/test/CodeGen/RISCV/rvv/abd.ll index 5e610c453e1bac..249a405c3470c6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/abd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/abd.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+experimental-zvabd -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVABD,ZVABD-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+experimental-zvabd -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVABD,ZVABD-RV64 ; ; SABD @@ -14,6 +16,12 @@ define <vscale x 16 x i8> @sabd_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_b: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e8, m2, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v10 +; ZVABD-NEXT: ret %a.sext = sext <vscale x 16 x i8> %a to <vscale x 16 x i16> %b.sext = sext <vscale x 16 x i8> %b to <vscale x 16 x i16> %sub = sub <vscale x 16 x i16> %a.sext, %b.sext @@ -30,6 +38,14 @@ define <vscale x 16 x i8> @sabd_b_promoted_ops(<vscale x 16 x i1> %a, <vscale x ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_b_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e8, m2, ta, ma +; ZVABD-NEXT: vmxor.mm v0, v0, v8 +; ZVABD-NEXT: vmv.v.i v8, 0 +; ZVABD-NEXT: vmerge.vim v8, v8, 1, v0 +; ZVABD-NEXT: ret %a.sext = sext <vscale x 16 x i1> %a to <vscale x 16 x i8> %b.sext = sext <vscale x 16 x i1> %b to <vscale x 16 x i8> %sub = sub <vscale x 16 x i8> %a.sext, %b.sext @@ -45,6 +61,12 @@ define <vscale x 8 x i16> @sabd_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_h: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e16, m2, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v10 +; ZVABD-NEXT: ret %a.sext = sext <vscale x 8 x i16> %a to <vscale x 8 x i32> %b.sext = sext <vscale x 8 x i16> %b to <vscale x 8 x i32> %sub = sub <vscale x 8 x i32> %a.sext, %b.sext @@ -63,6 +85,14 @@ define <vscale x 8 x i16> @sabd_h_promoted_ops(<vscale x 8 x i8> %a, <vscale x 8 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_h_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e8, m1, ta, ma +; ZVABD-NEXT: vabd.vv v10, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v10 +; ZVABD-NEXT: ret %a.sext = sext <vscale x 8 x i8> %a to <vscale x 8 x i16> %b.sext = sext <vscale x 8 x i8> %b to <vscale x 8 x i16> %sub = sub <vscale x 8 x i16> %a.sext, %b.sext @@ -78,6 +108,12 @@ define <vscale x 4 x i32> @sabd_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_s: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e32, m2, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v10 +; ZVABD-NEXT: ret %a.sext = sext <vscale x 4 x i32> %a to <vscale x 4 x i64> %b.sext = sext <vscale x 4 x i32> %b to <vscale x 4 x i64> %sub = sub <vscale x 4 x i64> %a.sext, %b.sext @@ -96,6 +132,14 @@ define <vscale x 4 x i32> @sabd_s_promoted_ops(<vscale x 4 x i16> %a, <vscale x ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_s_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e16, m1, ta, ma +; ZVABD-NEXT: vabd.vv v10, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e32, m2, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v10 +; ZVABD-NEXT: ret %a.sext = sext <vscale x 4 x i16> %a to <vscale x 4 x i32> %b.sext = sext <vscale x 4 x i16> %b to <vscale x 4 x i32> %sub = sub <vscale x 4 x i32> %a.sext, %b.sext @@ -123,6 +167,14 @@ define <vscale x 2 x i64> @sabd_d_promoted_ops(<vscale x 2 x i32> %a, <vscale x ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_d_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e32, m1, ta, ma +; ZVABD-NEXT: vabd.vv v10, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e64, m2, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v10 +; ZVABD-NEXT: ret %a.sext = sext <vscale x 2 x i32> %a to <vscale x 2 x i64> %b.sext = sext <vscale x 2 x i32> %b to <vscale x 2 x i64> %sub = sub <vscale x 2 x i64> %a.sext, %b.sext @@ -142,6 +194,12 @@ define <vscale x 16 x i8> @uabd_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) ; CHECK-NEXT: vmaxu.vv v8, v8, v10 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_b: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e8, m2, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v10 +; ZVABD-NEXT: ret %a.zext = zext <vscale x 16 x i8> %a to <vscale x 16 x i16> %b.zext = zext <vscale x 16 x i8> %b to <vscale x 16 x i16> %sub = sub <vscale x 16 x i16> %a.zext, %b.zext @@ -158,6 +216,14 @@ define <vscale x 16 x i8> @uabd_b_promoted_ops(<vscale x 16 x i1> %a, <vscale x ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_b_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e8, m2, ta, ma +; ZVABD-NEXT: vmxor.mm v0, v0, v8 +; ZVABD-NEXT: vmv.v.i v8, 0 +; ZVABD-NEXT: vmerge.vim v8, v8, 1, v0 +; ZVABD-NEXT: ret %a.zext = zext <vscale x 16 x i1> %a to <vscale x 16 x i8> %b.zext = zext <vscale x 16 x i1> %b to <vscale x 16 x i8> %sub =... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/124239 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
