https://github.com/CarolineConcatto updated
https://github.com/llvm/llvm-project/pull/121947
>From fca9d22fbfe55f1b9da5b205c1726d95eb94f176 Mon Sep 17 00:00:00 2001
From: Caroline Concatto <caroline.conca...@arm.com>
Date: Fri, 3 Jan 2025 13:52:55 +0000
Subject: [PATCH 1/3] [Clang][LLVM][AArch64]Add new feature SSVE-BitPerm
The 20204-12 ISA update release adds a new feature:
FEAT_SSVE_BitPerm, which allows the sve-bitperm instructions to run
in streaming mode.
It also removes the requirement of FEAT_SVE2 for FEAT_SVE_BitPerm.
The sve2-bitperm feature is now an alias for sve-bitperm and sve2.
A new feature flag sve-bitperm is added to reflect the change that the
instructions under
FEAT_SVE_BitPerm are supported if:
on non streaming mode with FEAT_SVE2 and FEAT_SVE_BitPerm or
in streaming mode with FEAT_SME and FEAT_SSVE_BitPerm
---
clang/include/clang/Basic/arm_sve.td | 2 +-
clang/lib/Basic/Targets/AArch64.cpp | 10 +-
clang/lib/Basic/Targets/AArch64.h | 2 +-
clang/test/CodeGen/AArch64/fmv-dependencies.c | 2 +-
.../AArch64/sve2-intrinsics/acle_sve2_bdep.c | 8 +-
.../AArch64/sve2-intrinsics/acle_sve2_bext.c | 8 +-
.../AArch64/sve2-intrinsics/acle_sve2_bgrp.c | 8 +-
clang/test/CodeGen/AArch64/targetattr.c | 2 +-
.../Driver/aarch64-implied-sme-features.c | 5 +-
.../Driver/aarch64-implied-sve-features.c | 14 ++-
.../print-supported-extensions-aarch64.c | 4 +-
.../Preprocessor/aarch64-target-features.c | 7 +-
.../acle_sve2_aes_bitperm_sha3_sm4.cpp | 96 +++++++++----------
llvm/lib/Target/AArch64/AArch64.td | 4 +-
llvm/lib/Target/AArch64/AArch64Features.td | 9 +-
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 8 +-
llvm/lib/Target/AArch64/AArch64Processors.td | 36 +++----
.../lib/Target/AArch64/AArch64SVEInstrInfo.td | 2 +-
.../AArch64/AsmParser/AArch64AsmParser.cpp | 4 +-
llvm/lib/TargetParser/AArch64TargetParser.cpp | 3 +
llvm/test/MC/AArch64/SVE2/bdep-diagnostics.s | 2 +-
llvm/test/MC/AArch64/SVE2/bdep.s | 8 +-
llvm/test/MC/AArch64/SVE2/bext.s | 8 +-
llvm/test/MC/AArch64/SVE2/bgrp.s | 8 +-
.../MC/AArch64/SVE2/directive-arch-negative.s | 12 ++-
llvm/test/MC/AArch64/SVE2/directive-arch.s | 6 +-
.../SVE2/directive-arch_extension-negative.s | 2 +-
.../AArch64/SVE2/directive-arch_extension.s | 2 +-
.../MC/AArch64/SVE2/directive-cpu-negative.s | 12 ++-
llvm/test/MC/AArch64/SVE2/directive-cpu.s | 6 +-
.../TargetParser/TargetParserTest.cpp | 33 ++++---
31 files changed, 193 insertions(+), 140 deletions(-)
diff --git a/clang/include/clang/Basic/arm_sve.td
b/clang/include/clang/Basic/arm_sve.td
index 1c6bdb8cad2d19..47f1754aeb6299 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1988,7 +1988,7 @@ def SVSM4E : SInst<"svsm4e[_{d}]", "ddd", "Ui",
MergeNone, "aarch64_sve_sm
def SVSM4EKEY : SInst<"svsm4ekey[_{d}]", "ddd", "Ui", MergeNone,
"aarch64_sve_sm4ekey", [IsOverloadNone]>;
}
-let SVETargetGuard = "sve2-bitperm", SMETargetGuard = InvalidMode in {
+let SVETargetGuard = "sve2,sve-bitperm", SMETargetGuard = InvalidMode in {
def SVBDEP : SInst<"svbdep[_{d}]", "ddd", "UcUsUiUl", MergeNone,
"aarch64_sve_bdep_x">;
def SVBDEP_N : SInst<"svbdep[_n_{d}]", "dda", "UcUsUiUl", MergeNone,
"aarch64_sve_bdep_x">;
def SVBEXT : SInst<"svbext[_{d}]", "ddd", "UcUsUiUl", MergeNone,
"aarch64_sve_bext_x">;
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 53e102bbe44687..ae55b8d9ab308d 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -485,7 +485,7 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
if (HasSVE2 && HasSVEAES)
Builder.defineMacro("__ARM_FEATURE_SVE2_AES", "1");
- if (HasSVE2 && HasSVE2BitPerm)
+ if (HasSVE2 && HasSVEBitPerm)
Builder.defineMacro("__ARM_FEATURE_SVE2_BITPERM", "1");
if (HasSVE2 && HasSVE2SHA3)
@@ -769,7 +769,7 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const
{
.Case("f64mm", FPU & SveMode && HasMatmulFP64)
.Case("sve2", FPU & SveMode && HasSVE2)
.Case("sve-aes", HasSVEAES)
- .Case("sve2-bitperm", FPU & SveMode && HasSVE2BitPerm)
+ .Case("sve-bitperm", FPU & HasSVEBitPerm)
.Case("sve2-sha3", FPU & SveMode && HasSVE2SHA3)
.Case("sve2-sm4", FPU & SveMode && HasSVE2SM4)
.Case("sve2p1", FPU & SveMode && HasSVE2p1)
@@ -881,12 +881,10 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
}
if (Feature == "+sve-b16b16")
HasSVEB16B16 = true;
- if (Feature == "+sve2-bitperm") {
+ if (Feature == "+sve-bitperm") {
FPU |= NeonMode;
- FPU |= SveMode;
HasFullFP16 = true;
- HasSVE2 = true;
- HasSVE2BitPerm = true;
+ HasSVEBitPerm = true;
}
if (Feature == "+f32mm") {
FPU |= NeonMode;
diff --git a/clang/lib/Basic/Targets/AArch64.h
b/clang/lib/Basic/Targets/AArch64.h
index 68a8b1ebad8cde..688966f0a25497 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -82,7 +82,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public
TargetInfo {
bool HasSVE2SHA3 = false;
bool HasSVE2SM4 = false;
bool HasSVEB16B16 = false;
- bool HasSVE2BitPerm = false;
+ bool HasSVEBitPerm = false;
bool HasMatmulFP64 = false;
bool HasMatmulFP32 = false;
bool HasLSE = false;
diff --git a/clang/test/CodeGen/AArch64/fmv-dependencies.c
b/clang/test/CodeGen/AArch64/fmv-dependencies.c
index 097b85e989d86b..de727fe10d0c61 100644
--- a/clang/test/CodeGen/AArch64/fmv-dependencies.c
+++ b/clang/test/CodeGen/AArch64/fmv-dependencies.c
@@ -192,7 +192,7 @@ int caller() {
// CHECK: attributes #[[sve]] = { {{.*}}
"target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a"
// CHECK: attributes #[[sve2]] = { {{.*}}
"target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+v8a"
// CHECK: attributes #[[sve2_aes]] = { {{.*}}
"target-features"="+aes,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve-aes,+sve2,+sve2-aes,+v8a"
-// CHECK: attributes #[[sve2_bitperm]] = { {{.*}}
"target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-bitperm,+v8a"
+// CHECK: attributes #[[sve2_bitperm]] = { {{.*}}
"target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve-bitperm,+sve2,+v8a"
// CHECK: attributes #[[sve2_sha3]] = { {{.*}}
"target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sha2,+sha3,+sve,+sve2,+sve2-sha3,+v8a"
// CHECK: attributes #[[sve2_sm4]] = { {{.*}}
"target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sm4,+sve,+sve2,+sve2-sm4,+v8a"
// CHECK: attributes #[[wfxt]] = { {{.*}}
"target-features"="+fp-armv8,+neon,+outline-atomics,+v8a,+wfxt"
diff --git a/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_bdep.c
b/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_bdep.c
index d7c070d412a8f7..d4681394a05089 100644
--- a/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_bdep.c
+++ b/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_bdep.c
@@ -1,10 +1,10 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature
+sve -target-feature +sve2 -target-feature +sve2-bitperm -O1 -Werror -Wall
-emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature
+sve -target-feature +sve2 -target-feature +sve2-bitperm -O1 -Werror -Wall
-emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple
aarch64 -target-feature +sve -target-feature +sve2 -target-feature
+sve2-bitperm -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple
aarch64 -target-feature +sve -target-feature +sve2 -target-feature
+sve2-bitperm -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s
-check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature
+sve -target-feature +sve2 -target-feature +sve-bitperm -O1 -Werror -Wall
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature
+sve -target-feature +sve2 -target-feature +sve-bitperm -O1 -Werror -Wall
-emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple
aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve-bitperm
-O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple
aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve-bitperm
-O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s
-check-prefix=CPP-CHECK
#include <arm_sve.h>
diff --git a/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_bext.c
b/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_bext.c
index 30b798e21f7a1d..6d654b9353e7af 100644
--- a/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_bext.c
+++ b/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_bext.c
@@ -1,10 +1,10 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature
+sve -target-feature +sve2 -target-feature +sve2-bitperm -O1 -Werror -Wall
-emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature
+sve -target-feature +sve2 -target-feature +sve2-bitperm -O1 -Werror -Wall
-emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple
aarch64 -target-feature +sve -target-feature +sve2 -target-feature
+sve2-bitperm -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple
aarch64 -target-feature +sve -target-feature +sve2 -target-feature
+sve2-bitperm -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s
-check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature
+sve -target-feature +sve2 -target-feature +sve-bitperm -O1 -Werror -Wall
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature
+sve -target-feature +sve2 -target-feature +sve-bitperm -O1 -Werror -Wall
-emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple
aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve-bitperm
-O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple
aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve-bitperm
-O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s
-check-prefix=CPP-CHECK
#include <arm_sve.h>
diff --git a/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_bgrp.c
b/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_bgrp.c
index 58445c6b810c71..a98d8e8a2b37c3 100644
--- a/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_bgrp.c
+++ b/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_bgrp.c
@@ -1,10 +1,10 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature
+sve -target-feature +sve2 -target-feature +sve2-bitperm -O1 -Werror -Wall
-emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature
+sve -target-feature +sve2 -target-feature +sve2-bitperm -O1 -Werror -Wall
-emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple
aarch64 -target-feature +sve -target-feature +sve2 -target-feature
+sve2-bitperm -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple
aarch64 -target-feature +sve -target-feature +sve2 -target-feature
+sve2-bitperm -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s
-check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature
+sve -target-feature +sve2 -target-feature +sve-bitperm -O1 -Werror -Wall
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature
+sve -target-feature +sve2 -target-feature +sve-bitperm -O1 -Werror -Wall
-emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple
aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve-bitperm
-O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple
aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve-bitperm
-O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s
-check-prefix=CPP-CHECK
#include <arm_sve.h>
diff --git a/clang/test/CodeGen/AArch64/targetattr.c
b/clang/test/CodeGen/AArch64/targetattr.c
index ee7a07244ef9aa..f8d5f9912c0d71 100644
--- a/clang/test/CodeGen/AArch64/targetattr.c
+++ b/clang/test/CodeGen/AArch64/targetattr.c
@@ -204,7 +204,7 @@ void applem4() {}
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a"
}
// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a"
}
// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
}
-// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-cpu"="cortex-a710"
"target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve2,+sve2-bitperm,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a"
}
+// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-cpu"="cortex-a710"
"target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve-bitperm,+sve2,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a"
}
// CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR6]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-cpu"="generic" "target-features"="+ete,+fp-armv8,+neon,+trbe,+v8a" }
// CHECK: attributes #[[ATTR7]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"tune-cpu"="generic" }
diff --git a/clang/test/Driver/aarch64-implied-sme-features.c
b/clang/test/Driver/aarch64-implied-sme-features.c
index 4d507c0e99dd91..23ec27ff1aaffb 100644
--- a/clang/test/Driver/aarch64-implied-sme-features.c
+++ b/clang/test/Driver/aarch64-implied-sme-features.c
@@ -51,4 +51,7 @@
// SME-SUBFEATURE-CONFLICT-REV: "-target-feature" "+bf16"{{.*}}
"-target-feature" "+sme" "-target-feature" "+sme-i16i64"
// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+ssve-aes %s -### 2>&1
| FileCheck %s --check-prefix=SVE-AES
-// SVE-AES: "-target-feature" "+sme" "-target-feature" "+sme2"
"-target-feature" "+ssve-aes" "-target-feature" "+sve-aes"
\ No newline at end of file
+// SVE-AES: "-target-feature" "+sme" "-target-feature" "+sme2"
"-target-feature" "+ssve-aes" "-target-feature" "+sve-aes"
+
++// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+ssve-bitperm %s -###
2>&1 | FileCheck %s --check-prefix=SVE-BITPERM
++// SVE-BITPERM: "-target-feature" "+sme" "-target-feature" "+sme2"
"-target-feature" "+ssve-bitperm" "-target-feature" "+sve-bitperm"
diff --git a/clang/test/Driver/aarch64-implied-sve-features.c
b/clang/test/Driver/aarch64-implied-sve-features.c
index e5f1e553454143..01ce8d557ba7e7 100644
--- a/clang/test/Driver/aarch64-implied-sve-features.c
+++ b/clang/test/Driver/aarch64-implied-sve-features.c
@@ -23,17 +23,24 @@
// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve+sve2 %s -### 2>&1
| FileCheck %s --check-prefix=SVE-SVE2
// SVE-SVE2: "-target-feature" "+sve" "-target-feature" "+sve2"
+// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve-bitperm %s -###
2>&1 | FileCheck %s --check-prefix=SVE-BITPERM
+// SVE-BITPERM: "-target-feature" "+sve-bitperm"
+
// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-bitperm %s -###
2>&1 | FileCheck %s --check-prefix=SVE2-BITPERM
-// SVE2-BITPERM: "-target-feature" "+sve" "-target-feature" "+sve2"
"-target-feature" "+sve2-bitperm"
+// SVE2-BITPERM: "-target-feature" "+sve" "-target-feature" "+sve-bitperm"
"-target-feature" "+sve2" "-target-feature" "+sve2-bitperm"
// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+nosve2-bitperm %s
-### 2>&1 | FileCheck %s --check-prefix=NOSVE2-BITPERM
+// NOSVE2-BITPERM-NOT: "-target-feature" "+sve-bitperm"
// NOSVE2-BITPERM-NOT: "-target-feature" "+sve2-bitperm"
// NOSVE2-BITPERM-NOT: "-target-feature" "+sve2"
// NOSVE2-BITPERM-NOT: "-target-feature" "+sve"
// NOSVE2-BITPERM-NOT: sve2-bitperm"
+// RUN: %clang --target=aarch64-linux-gnu
-march=armv8-a+sve-bitperm+nosve-bitperm %s -### 2>&1 | FileCheck %s
--check-prefix=SVE-BITPERM-REVERT
+// SVE-BITPERM-REVERT: "-target-feature" "-sve-bitperm"
+
// RUN: %clang --target=aarch64-linux-gnu
-march=armv8-a+sve2-bitperm+nosve2-bitperm %s -### 2>&1 | FileCheck %s
--check-prefix=SVE2-BITPERM-REVERT
-// SVE2-BITPERM-REVERT: "-target-feature" "+sve" "-target-feature" "+sve2"
"-target-feature" "-sve2-bitperm"
+// SVE2-BITPERM-REVERT: "-target-feature" "+sve" "-target-feature"
"-sve-bitperm" "-target-feature" "+sve2" "-target-feature" "-sve2-bitperm"
// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-aes+nosve2-aes
%s -### 2>&1 | FileCheck %s --check-prefix=SVE2-AES-REVERT
// SVE2-AES-REVERT: "-target-feature" "+sve" "-target-feature" "-sve-aes"
"-target-feature" "+sve2" "-target-feature" "-sve2-aes"
@@ -57,7 +64,7 @@
// SVE2-SM4: "-target-feature" "+sve" "-target-feature" "+sve2"
"-target-feature" "+sve2-sm4"
// RUN: %clang --target=aarch64-linux-gnu
-march=armv8-a+sve2-bitperm+nosve2-aes %s -### 2>&1 | FileCheck %s
--check-prefix=SVE2-SUBFEATURE-MIX
-// SVE2-SUBFEATURE-MIX: "-target-feature" "+sve" "-target-feature" "+sve2"
"-target-feature" "+sve2-bitperm"
+// SVE2-SUBFEATURE-MIX: "-target-feature" "+sve" "-target-feature"
"+sve-bitperm" "-target-feature" "+sve2" "-target-feature" "+sve2-bitperm"
// SVE2-SUBFEATURE-NOT: sve2-aes
// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sm4+nosve2 %s
-### 2>&1 | FileCheck %s --check-prefix=SVE2-SUBFEATURE-CONFLICT
@@ -72,6 +79,7 @@
// SVE-SUBFEATURE-CONFLICT-REV: "-target-feature" "+sve" "-target-feature"
"+sve-aes" "-target-feature" "+sve2" "-target-feature" "+sve2-aes"
// RUN: %clang --target=aarch64-linux-gnu -mcpu=neoverse-n2+nosve2 %s -###
2>&1 | FileCheck %s --check-prefix=SVE-MCPU-FEATURES
+// SVE-MCPU-FEATURES-NOT: "-target-feature" "+sve-bitperm"
// SVE-MCPU-FEATURES-NOT: "-target-feature" "+sve2-bitperm"
// SVE-MCPU-FEATURES-NOT: "-target-feature" "+sve2"
// SVE-MCPU-FEATURES: "-target-feature" "+sve"
diff --git a/clang/test/Driver/print-supported-extensions-aarch64.c
b/clang/test/Driver/print-supported-extensions-aarch64.c
index 09d499548aa565..75aa1a3aeecdde 100644
--- a/clang/test/Driver/print-supported-extensions-aarch64.c
+++ b/clang/test/Driver/print-supported-extensions-aarch64.c
@@ -78,6 +78,7 @@
// CHECK-NEXT: predres2 FEAT_SPECRES2
Enable Speculation Restriction Instruction
// CHECK-NEXT: ssbs FEAT_SSBS, FEAT_SSBS2
Enable Speculative Store Bypass Safe bit
// CHECK-NEXT: ssve-aes FEAT_SSVE_AES
Enable Armv9.6-A SVE AES support in streaming SVE mode
+// CHECK-NEXT: ssve-bitperm FEAT_SSVE_BitPerm
Enable Armv9.6-A SVE BitPerm support in streaming SVE mode
// CHECK-NEXT: ssve-fp8dot2 FEAT_SSVE_FP8DOT2
Enable SVE2 FP8 2-way dot product instructions
// CHECK-NEXT: ssve-fp8dot4 FEAT_SSVE_FP8DOT4
Enable SVE2 FP8 4-way dot product instructions
// CHECK-NEXT: ssve-fp8fma FEAT_SSVE_FP8FMA
Enable SVE2 FP8 multiply-add instructions
@@ -86,10 +87,11 @@
// CHECK-NEXT: sve-aes2 FEAT_SVE_AES2
Enable Armv9.6-A SVE multi-vector AES and multi-vector quadword
polynomial multiply instructions
// CHECK-NEXT: sve-b16b16 FEAT_SVE_B16B16
Enable SVE2 non-widening and SME2 Z-targeting non-widening
BFloat16 instructions
// CHECK-NEXT: sve-bfscale FEAT_SVE_BFSCALE
Enable Armv9.6-A SVE BFloat16 scaling instructions
+// CHECK-NEXT: sve-bitperm FEAT_SVE_BitPerm
Enable bit permutation SVE2 instructions
// CHECK-NEXT: sve-f16f32mm FEAT_SVE_F16F32MM
Enable Armv9.6-A FP16 to FP32 Matrix Multiply
// CHECK-NEXT: sve2 FEAT_SVE2
Enable Scalable Vector Extension 2 (SVE2) instructions
// CHECK-NEXT: sve2-aes
Shorthand for +sve2+sve-aes
-// CHECK-NEXT: sve2-bitperm FEAT_SVE_BitPerm
Enable bit permutation SVE2 instructions
+// CHECK-NEXT: sve2-bitperm
Shorthand for +sve2+sve-bitperm
// CHECK-NEXT: sve2-sha3 FEAT_SVE_SHA3
Enable SHA3 SVE2 instructions
// CHECK-NEXT: sve2-sm4 FEAT_SVE_SM4
Enable SM4 SVE2 instructions
// CHECK-NEXT: sve2p1 FEAT_SVE2p1
Enable Scalable Vector Extension 2.1 instructions
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index 86265f630296c3..b10c55447d9afb 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -246,7 +246,12 @@
// CHECK-SVE2SHA3: __ARM_FEATURE_SVE2_SHA3 1
// RUN: %clang -target aarch64-none-linux-gnu -march=armv9-a+sve2-sm4 -x c -E
-dM %s -o - | FileCheck --check-prefix=CHECK-SVE2SM4 %s
// CHECK-SVE2SM4: __ARM_FEATURE_SVE2_SM4 1
-// RUN: %clang -target aarch64-none-linux-gnu -march=armv9-a+sve2-bitperm -x c
-E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2BITPERM %s
+// RUN: %clang -target aarch64-none-linux-gnu -march=armv9-a+sve-bitperm -x c
-E -dM %s -o - | FileCheck --check-prefix=CHECK-SVEBITPERM %s
+// CHECK-SVEBITPERM: __ARM_FEATURE_SVE2_BITPERM 1
+
+// RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+sve2-bitperm -x c
-E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2BITPERM %s
+// RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+sve-bitperm+sve2
-x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2BITPERM %s
+// CHECK-SVE2BITPERM: __ARM_FEATURE_SVE2 1
// CHECK-SVE2BITPERM: __ARM_FEATURE_SVE2_BITPERM 1
// RUN: %clang -target aarch64-none-linux-gnu -march=armv9-a+sve2p1 -x c -E
-dM %s -o - | FileCheck --check-prefix=CHECK-SVE2p1 %s
diff --git
a/clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_aes_bitperm_sha3_sm4.cpp
b/clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_aes_bitperm_sha3_sm4.cpp
index 93d4b007016937..985ea15ac2a4e3 100644
--- a/clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_aes_bitperm_sha3_sm4.cpp
+++ b/clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_aes_bitperm_sha3_sm4.cpp
@@ -26,61 +26,61 @@ void test(uint8_t u8, uint16_t u16, uint32_t u32, uint64_t
u64)
// expected-error@+2 {{'svaesmc_u8' needs target feature sve,sve2,sve-aes}}
// overload-error@+1 {{'svaesmc' needs target feature sve,sve2,sve-aes}}
SVE_ACLE_FUNC(svaesmc,_u8,,)(svundef_u8());
- // expected-error@+2 {{'svbdep_u8' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbdep' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbdep_u8' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbdep' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbdep,_u8,,)(svundef_u8(), svundef_u8());
- // expected-error@+2 {{'svbdep_n_u8' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbdep' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbdep_n_u8' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbdep' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbdep,_n_u8,,)(svundef_u8(), u8);
- // expected-error@+2 {{'svbext_u8' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbext' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbext_u8' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbext' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbext,_u8,,)(svundef_u8(), svundef_u8());
- // expected-error@+2 {{'svbext_n_u8' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbext' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbext_n_u8' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbext' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbext,_n_u8,,)(svundef_u8(), u8);
- // expected-error@+2 {{'svbgrp_u8' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbgrp' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbgrp_u8' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbgrp' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbgrp,_u8,,)(svundef_u8(), svundef_u8());
- // expected-error@+2 {{'svbgrp_n_u8' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbgrp' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbgrp_n_u8' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbgrp' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbgrp,_n_u8,,)(svundef_u8(), u8);
- // expected-error@+2 {{'svbdep_u16' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbdep' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbdep_u16' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbdep' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbdep,_u16,,)(svundef_u16(), svundef_u16());
- // expected-error@+2 {{'svbdep_n_u16' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbdep' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbdep_n_u16' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbdep' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbdep,_n_u16,,)(svundef_u16(), u16);
- // expected-error@+2 {{'svbext_u16' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbext' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbext_u16' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbext' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbext,_u16,,)(svundef_u16(), svundef_u16());
- // expected-error@+2 {{'svbext_n_u16' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbext' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbext_n_u16' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbext' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbext,_n_u16,,)(svundef_u16(), u16);
- // expected-error@+2 {{'svbgrp_u16' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbgrp' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbgrp_u16' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbgrp' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbgrp,_u16,,)(svundef_u16(), svundef_u16());
- // expected-error@+2 {{'svbgrp_n_u16' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbgrp' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbgrp_n_u16' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbgrp' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbgrp,_n_u16,,)(svundef_u16(), u16);
- // expected-error@+2 {{'svbdep_u32' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbdep' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbdep_u32' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbdep' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbdep,_u32,,)(svundef_u32(), svundef_u32());
- // expected-error@+2 {{'svbdep_n_u32' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbdep' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbdep_n_u32' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbdep' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbdep,_n_u32,,)(svundef_u32(), u32);
- // expected-error@+2 {{'svbext_u32' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbext' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbext_u32' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbext' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbext,_u32,,)(svundef_u32(), svundef_u32());
- // expected-error@+2 {{'svbext_n_u32' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbext' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbext_n_u32' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbext' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbext,_n_u32,,)(svundef_u32(), u32);
- // expected-error@+2 {{'svbgrp_u32' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbgrp' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbgrp_u32' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbgrp' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbgrp,_u32,,)(svundef_u32(), svundef_u32());
- // expected-error@+2 {{'svbgrp_n_u32' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbgrp' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbgrp_n_u32' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbgrp' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbgrp,_n_u32,,)(svundef_u32(), u32);
// expected-error@+2 {{'svsm4e_u32' needs target feature sve,sve2-sm4}}
// overload-error@+1 {{'svsm4e' needs target feature sve,sve2-sm4}}
@@ -89,23 +89,23 @@ void test(uint8_t u8, uint16_t u16, uint32_t u32, uint64_t
u64)
// overload-error@+1 {{'svsm4ekey' needs target feature sve,sve2-sm4}}
SVE_ACLE_FUNC(svsm4ekey,_u32,,)(svundef_u32(), svundef_u32());
- // expected-error@+2 {{'svbdep_u64' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbdep' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbdep_u64' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbdep' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbdep,_u64,,)(svundef_u64(), svundef_u64());
- // expected-error@+2 {{'svbdep_n_u64' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbdep' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbdep_n_u64' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbdep' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbdep,_n_u64,,)(svundef_u64(), u64);
- // expected-error@+2 {{'svbext_u64' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbext' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbext_u64' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbext' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbext,_u64,,)(svundef_u64(), svundef_u64());
- // expected-error@+2 {{'svbext_n_u64' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbext' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbext_n_u64' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbext' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbext,_n_u64,,)(svundef_u64(), u64);
- // expected-error@+2 {{'svbgrp_u64' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbgrp' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbgrp_u64' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbgrp' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbgrp,_u64,,)(svundef_u64(), svundef_u64());
- // expected-error@+2 {{'svbgrp_n_u64' needs target feature sve,sve2-bitperm}}
- // overload-error@+1 {{'svbgrp' needs target feature sve,sve2-bitperm}}
+ // expected-error@+2 {{'svbgrp_n_u64' needs target feature
sve,sve2,sve-bitperm}}
+ // overload-error@+1 {{'svbgrp' needs target feature sve,sve2,sve-bitperm}}
SVE_ACLE_FUNC(svbgrp,_n_u64,,)(svundef_u64(), u64);
// expected-error@+2 {{'svpmullb_pair_u64' needs target feature
sve,sve2,sve-aes}}
// overload-error@+1 {{'svpmullb_pair' needs target feature
sve,sve2,sve-aes}}
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index e3dd334e7b098b..20e77b3be2a272 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -63,7 +63,7 @@ def SVE2p1Unsupported : AArch64Unsupported;
def SVE2Unsupported : AArch64Unsupported {
let F = !listconcat([HasSVE2, HasSVE2orSME, HasSVE2orSME2, HasSSVE_FP8FMA,
HasSMEF8F16,
- HasSMEF8F32, HasSVEAES, HasSVE2SHA3, HasSVE2SM4,
HasSVE2BitPerm,
+ HasSMEF8F32, HasSVEAES, HasSVE2SHA3, HasSVE2SM4,
HasSVEBitPerm,
HasSVEB16B16],
SVE2p1Unsupported.F);
}
@@ -74,7 +74,7 @@ def SVEUnsupported : AArch64Unsupported {
}
let F = [HasSME2p2, HasSVE2p2orSME2p2, HasNonStreamingSVEorSME2p2,
- HasNonStreamingSVE2p2orSME2p2] in
+ HasNonStreamingSVE2p2orSME2p2, HasNonStreamingSVE2orSSVE_BitPerm] in
def SME2p2Unsupported : AArch64Unsupported;
def SME2p1Unsupported : AArch64Unsupported {
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td
b/llvm/lib/Target/AArch64/AArch64Features.td
index 41eb9a73bd013d..34432d8f37efa5 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -376,9 +376,11 @@ def FeatureSVE2SM4 : ExtensionWithMArch<"sve2-sm4",
"SVE2SM4", "FEAT_SVE_SM4",
def FeatureSVE2SHA3 : ExtensionWithMArch<"sve2-sha3", "SVE2SHA3",
"FEAT_SVE_SHA3",
"Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3]>;
+def FeatureSVEBitPerm : ExtensionWithMArch<"sve-bitperm", "SVEBitPerm",
+ "FEAT_SVE_BitPerm", "Enable bit permutation SVE2 instructions">;
+
def FeatureSVE2BitPerm : ExtensionWithMArch<"sve2-bitperm", "SVE2BitPerm",
- "FEAT_SVE_BitPerm",
- "Enable bit permutation SVE2 instructions", [FeatureSVE2]>;
+ "", "Shorthand for +sve2+sve-bitperm", [FeatureSVE2, FeatureSVEBitPerm]>;
def FeatureTRBE : Extension<"trbe", "TRBE", "FEAT_TRBE",
"Enable Trace Buffer Extension">;
@@ -565,6 +567,9 @@ def FeaturePCDPHINT: ExtensionWithMArch<"pcdphint",
"PCDPHINT", "FEAT_PCDPHINT",
def FeaturePoPS: ExtensionWithMArch<"pops", "PoPS", "FEAT_PoPS",
"Enable Armv9.6-A Point Of Physical Storage (PoPS) DC instructions">;
+def FeatureSSVE_BitPerm : ExtensionWithMArch<"ssve-bitperm", "SSVE_BitPerm",
"FEAT_SSVE_BitPerm",
+ "Enable Armv9.6-A SVE BitPerm support in streaming SVE mode", [FeatureSME2,
FeatureSVEBitPerm]>;
+
//===----------------------------------------------------------------------===//
// Other Features
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index c6f5cdcd1d5fe7..4414c49b65e572 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -155,8 +155,8 @@ def HasSVE2SM4 :
Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasS
AssemblerPredicateWithAll<(all_of
FeatureSVE2SM4), "sve2-sm4">;
def HasSVE2SHA3 : Predicate<"Subtarget->isSVEAvailable() &&
Subtarget->hasSVE2SHA3()">,
AssemblerPredicateWithAll<(all_of
FeatureSVE2SHA3), "sve2-sha3">;
-def HasSVE2BitPerm : Predicate<"Subtarget->isSVEAvailable() &&
Subtarget->hasSVE2BitPerm()">,
- AssemblerPredicateWithAll<(all_of
FeatureSVE2BitPerm), "sve2-bitperm">;
+def HasSVEBitPerm : Predicate<"Subtarget->isSVEAvailable() &&
Subtarget->hasSVEBitPerm()">,
+ AssemblerPredicateWithAll<(all_of
FeatureSVEBitPerm), "sve-bitperm">;
def HasSMEandIsNonStreamingSafe
: Predicate<"Subtarget->hasSME()">,
AssemblerPredicateWithAll<(all_of
FeatureSME), "sme">;
@@ -286,6 +286,10 @@ def HasNonStreamingSVE2p2orSME2p2
"(Subtarget->isSVEorStreamingSVEAvailable() &&
Subtarget->hasSME2p2())">,
AssemblerPredicateWithAll<(any_of FeatureSVE2p2,
FeatureSME2p2),
"sme2p2 or sve2p2">;
+def HasNonStreamingSVE2orSSVE_BitPerm
+ : Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE2()) ||"
+ "(Subtarget->isSVEorStreamingSVEAvailable() &&
Subtarget->hasSSVE_BitPerm())">,
+ AssemblerPredicateWithAll<(any_of FeatureSVE2,
FeatureSSVE_BitPerm), "sve2 or ssve-bitperm">;
// A subset of NEON instructions are legal in Streaming SVE execution mode,
// so don't need the additional check for 'isNeonAvailable'.
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td
b/llvm/lib/Target/AArch64/AArch64Processors.td
index 2da67126a17537..364ab0d82bf888 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -694,7 +694,7 @@ def ProcessorFeatures {
FeatureLSE, FeatureRAS, FeatureRDM];
list<SubtargetFeature> A510 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
FeatureMatMulInt8, FeatureBF16, FeatureAM,
- FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
+ FeatureMTE, FeatureETE, FeatureSVEBitPerm,
FeatureFP16FML,
FeatureCCIDX,
FeatureSB, FeaturePAuth, FeatureSSBS,
FeatureSVE, FeatureSVE2,
@@ -702,7 +702,7 @@ def ProcessorFeatures {
FeatureFPARMv8,FeatureFullFP16, FeatureJS,
FeatureLSE,
FeatureRAS, FeatureRCPC, FeatureRDM];
list<SubtargetFeature> A520 = [HasV9_2aOps, FeaturePerfMon, FeatureAM,
- FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
+ FeatureMTE, FeatureETE, FeatureSVEBitPerm,
FeatureFP16FML,
FeatureCCIDX,
FeatureSB, FeatureSSBS, FeaturePAuth,
FeatureFlagM, FeaturePredRes,
@@ -711,7 +711,7 @@ def ProcessorFeatures {
FeatureNEON, FeatureLSE, FeatureRAS,
FeatureRCPC, FeatureRDM,
FeatureDotProd];
list<SubtargetFeature> A520AE = [HasV9_2aOps, FeaturePerfMon, FeatureAM,
- FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
+ FeatureMTE, FeatureETE, FeatureSVEBitPerm,
FeatureFP16FML,
FeatureCCIDX,
FeatureSB, FeatureSSBS, FeaturePAuth,
FeatureFlagM, FeaturePredRes,
@@ -747,14 +747,14 @@ def ProcessorFeatures {
list<SubtargetFeature> A710 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
FeatureCCIDX, FeatureSSBS,
FeatureETE, FeatureMTE, FeatureFP16FML,
- FeatureSVE2BitPerm, FeatureBF16,
FeatureMatMulInt8,
+ FeatureSVEBitPerm, FeatureBF16,
FeatureMatMulInt8,
FeaturePAuth, FeatureFlagM, FeatureSB,
FeatureSVE, FeatureSVE2,
FeatureComplxNum, FeatureCRC, FeatureDotProd,
FeatureFPARMv8,
FeatureFullFP16, FeatureJS, FeatureLSE,
FeatureRAS, FeatureRCPC, FeatureRDM];
list<SubtargetFeature> A715 = [HasV9_0aOps, FeatureNEON, FeatureMTE,
FeatureCCIDX,
FeatureFP16FML, FeatureSVE, FeatureTRBE,
- FeatureSVE2BitPerm, FeatureBF16, FeatureETE,
+ FeatureSVEBitPerm, FeatureBF16, FeatureETE,
FeaturePerfMon, FeatureMatMulInt8, FeatureSPE,
FeatureSB, FeatureSSBS, FeatureFullFP16,
FeaturePAuth, FeaturePredRes, FeatureFlagM,
FeatureSVE2, FeatureComplxNum, FeatureCRC,
@@ -763,7 +763,7 @@ def ProcessorFeatures {
FeatureRCPC, FeatureRDM];
list<SubtargetFeature> A720 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
FeatureCCIDX,
- FeatureTRBE, FeatureSVE2BitPerm, FeatureETE,
+ FeatureTRBE, FeatureSVEBitPerm, FeatureETE,
FeaturePerfMon, FeatureSPE, FeatureSPE_EEF,
FeatureSB, FeatureSSBS, FeaturePAuth,
FeatureFlagM, FeaturePredRes,
FeatureSVE, FeatureSVE2, FeatureBF16,
FeatureComplxNum, FeatureCRC,
@@ -772,7 +772,7 @@ def ProcessorFeatures {
FeatureRCPC, FeatureRDM];
list<SubtargetFeature> A720AE = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
FeatureCCIDX,
- FeatureTRBE, FeatureSVE2BitPerm, FeatureETE,
+ FeatureTRBE, FeatureSVEBitPerm, FeatureETE,
FeaturePerfMon, FeatureSPE, FeatureSPE_EEF,
FeatureSB, FeatureSSBS, FeaturePAuth,
FeatureFlagM, FeaturePredRes,
FeatureSVE, FeatureSVE2, FeatureBF16,
FeatureComplxNum, FeatureCRC,
@@ -782,7 +782,7 @@ def ProcessorFeatures {
list<SubtargetFeature> A725 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
FeatureCCIDX,
FeatureETE, FeaturePerfMon, FeatureSPE,
- FeatureSVE2BitPerm, FeatureSPE_EEF,
FeatureTRBE,
+ FeatureSVEBitPerm, FeatureSPE_EEF,
FeatureTRBE,
FeatureFlagM, FeaturePredRes, FeatureSB,
FeatureSSBS,
FeatureSVE, FeatureSVE2, FeatureBF16,
FeatureComplxNum, FeatureCRC,
FeatureDotProd, FeatureFPARMv8,
FeatureFullFP16, FeatureMatMulInt8,
@@ -814,7 +814,7 @@ def ProcessorFeatures {
FeatureRCPC, FeatureCRC, FeatureLSE,
FeatureRAS, FeatureRDM];
list<SubtargetFeature> X2 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
FeatureMatMulInt8, FeatureBF16, FeatureAM,
- FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
+ FeatureMTE, FeatureETE, FeatureSVEBitPerm,
FeatureFP16FML,
FeatureCCIDX,
FeaturePAuth, FeatureSSBS, FeatureSB,
FeatureSVE, FeatureSVE2, FeatureFlagM,
@@ -823,7 +823,7 @@ def ProcessorFeatures {
list<SubtargetFeature> X3 = [HasV9_0aOps, FeatureSVE, FeatureNEON,
FeaturePerfMon, FeatureETE, FeatureTRBE,
FeatureSPE, FeatureBF16, FeatureMatMulInt8,
- FeatureMTE, FeatureSVE2BitPerm,
FeatureFullFP16,
+ FeatureMTE, FeatureSVEBitPerm,
FeatureFullFP16,
FeatureFP16FML,
FeatureCCIDX,
FeatureSB, FeaturePAuth, FeaturePredRes,
FeatureFlagM, FeatureSSBS,
@@ -831,7 +831,7 @@ def ProcessorFeatures {
FeatureLSE, FeatureRAS, FeatureRCPC,
FeatureRDM, FeatureDotProd];
list<SubtargetFeature> X4 = [HasV9_2aOps,
FeaturePerfMon, FeatureETE, FeatureTRBE,
- FeatureSPE, FeatureMTE, FeatureSVE2BitPerm,
+ FeatureSPE, FeatureMTE, FeatureSVEBitPerm,
FeatureFP16FML, FeatureSPE_EEF,
FeatureCCIDX,
FeatureSB, FeatureSSBS, FeaturePAuth,
FeatureFlagM, FeaturePredRes,
@@ -841,7 +841,7 @@ def ProcessorFeatures {
list<SubtargetFeature> X925 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
FeatureCCIDX,
FeatureETE, FeaturePerfMon, FeatureSPE,
- FeatureSVE2BitPerm, FeatureSPE_EEF,
FeatureTRBE,
+ FeatureSVEBitPerm, FeatureSPE_EEF,
FeatureTRBE,
FeatureFlagM, FeaturePredRes, FeatureSB,
FeatureSSBS,
FeatureSVE, FeatureSVE2, FeatureBF16,
FeatureComplxNum, FeatureCRC,
FeatureDotProd, FeatureFPARMv8,
FeatureFullFP16, FeatureMatMulInt8,
@@ -855,7 +855,7 @@ def ProcessorFeatures {
FeatureFPAC, FeatureFP16FML, FeatureRandGen,
FeatureSSBS, FeatureLS64, FeatureCLRBHB,
FeatureSPECRES2, FeatureSVEAES,
FeatureSVE2SM4,
- FeatureSVE2SHA3, FeatureSVE2BitPerm,
FeatureETE,
+ FeatureSVE2SHA3, FeatureSVE2,
FeatureSVEBitPerm, FeatureETE,
FeatureMEC, FeatureFP8DOT2];
list<SubtargetFeature> Carmel = [HasV8_2aOps, FeatureNEON, FeatureSHA2,
FeatureAES,
FeatureFullFP16, FeatureCRC, FeatureLSE,
FeatureRAS, FeatureRDM,
@@ -942,7 +942,7 @@ def ProcessorFeatures {
FeaturePerfMon, FeatureCRC, FeatureLSE,
FeatureRAS, FeatureRDM];
list<SubtargetFeature> NeoverseN2 = [HasV9_0aOps, FeatureBF16, FeatureETE,
FeatureFP16FML,
FeatureMatMulInt8, FeatureMTE,
FeatureSVE2,
- FeatureSVE2BitPerm, FeatureTRBE,
+ FeatureSVEBitPerm, FeatureTRBE,
FeaturePerfMon,
FeatureCCIDX,
FeatureDotProd, FeatureFullFP16,
FeatureSB, FeatureSSBS, FeatureSVE,
@@ -951,7 +951,7 @@ def ProcessorFeatures {
list<SubtargetFeature> NeoverseN3 = [HasV9_2aOps, FeatureETE, FeatureFP16FML,
FeatureFullFP16, FeatureMTE,
FeaturePerfMon,
FeatureRandGen, FeatureSPE,
FeatureSPE_EEF,
- FeatureSVE2BitPerm,
+ FeatureSVEBitPerm,
FeatureCCIDX,
FeatureSSBS, FeatureSB, FeaturePredRes,
FeaturePAuth, FeatureFlagM,
FeatureSVE, FeatureSVE2, FeatureBF16,
FeatureComplxNum,
@@ -978,7 +978,7 @@ def ProcessorFeatures {
FeatureRCPC, FeatureRDM];
list<SubtargetFeature> NeoverseV2 = [HasV9_0aOps, FeatureBF16, FeatureSPE,
FeaturePerfMon, FeatureETE,
FeatureMatMulInt8,
- FeatureNEON, FeatureSVE2BitPerm,
FeatureFP16FML,
+ FeatureNEON, FeatureSVEBitPerm,
FeatureFP16FML,
FeatureMTE, FeatureRandGen,
FeatureCCIDX,
FeatureSVE, FeatureSVE2, FeatureSSBS,
FeatureFullFP16, FeatureDotProd,
@@ -988,7 +988,7 @@ def ProcessorFeatures {
FeatureFullFP16, FeatureLS64, FeatureMTE,
FeaturePerfMon, FeatureRandGen,
FeatureSPE,
FeatureCCIDX,
- FeatureSPE_EEF, FeatureSVE2BitPerm,
FeatureBRBE,
+ FeatureSPE_EEF, FeatureSVEBitPerm,
FeatureBRBE,
FeatureSSBS, FeatureSB, FeaturePredRes,
FeaturePAuth, FeatureFlagM,
FeatureSVE, FeatureSVE2, FeatureBF16,
FeatureComplxNum, FeatureCRC,
FeatureDotProd, FeatureFPARMv8,
FeatureMatMulInt8, FeatureJS, FeatureLSE,
@@ -996,7 +996,7 @@ def ProcessorFeatures {
list<SubtargetFeature> NeoverseV3AE = [HasV9_2aOps, FeatureETE,
FeatureFP16FML,
FeatureFullFP16, FeatureLS64, FeatureMTE,
FeaturePerfMon, FeatureRandGen,
FeatureSPE,
- FeatureSPE_EEF, FeatureSVE2BitPerm,
FeatureBRBE,
+ FeatureSPE_EEF, FeatureSVEBitPerm,
FeatureBRBE,
FeatureSSBS, FeatureSB, FeaturePredRes,
FeaturePAuth, FeatureFlagM,
FeatureCCIDX,
FeatureSVE, FeatureSVE2, FeatureBF16,
FeatureComplxNum, FeatureCRC,
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 7dd6d49bf20227..bb17ddaa5e3f5b 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -3946,7 +3946,7 @@ let Predicates = [HasSVE2SHA3] in {
defm RAX1_ZZZ_D : sve2_crypto_cons_bin_op<0b1, "rax1", ZPR64,
int_aarch64_sve_rax1, nxv2i64>;
} // End HasSVE2SHA3
-let Predicates = [HasSVE2BitPerm] in {
+let Predicates = [HasSVEBitPerm, HasNonStreamingSVE2orSSVE_BitPerm] in {
// SVE2 bitwise permute
defm BEXT_ZZZ : sve2_misc_bitwise<0b1100, "bext", int_aarch64_sve_bext_x>;
defm BDEP_ZZZ : sve2_misc_bitwise<0b1101, "bdep", int_aarch64_sve_bdep_x>;
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index f44afd804c2bde..51eba029e127df 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3755,7 +3755,8 @@ static const struct Extension {
{"sve2-aes", {AArch64::FeatureAliasSVE2AES, AArch64::FeatureSVEAES}},
{"sve2-sm4", {AArch64::FeatureSVE2SM4}},
{"sve2-sha3", {AArch64::FeatureSVE2SHA3}},
- {"sve2-bitperm", {AArch64::FeatureSVE2BitPerm}},
+ {"sve-bitperm", {AArch64::FeatureSVEBitPerm}},
+ {"sve2-bitperm", {AArch64::FeatureSVE2BitPerm,
AArch64::FeatureSVEBitPerm}},
{"sve2p1", {AArch64::FeatureSVE2p1}},
{"ls64", {AArch64::FeatureLS64}},
{"xs", {AArch64::FeatureXS}},
@@ -3827,6 +3828,7 @@ static const struct Extension {
{"lsui", {AArch64::FeatureLSUI}},
{"occmo", {AArch64::FeatureOCCMO}},
{"pcdphint", {AArch64::FeaturePCDPHINT}},
+ {"ssve-bitperm", {AArch64::FeatureSSVE_BitPerm}},
};
static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp
b/llvm/lib/TargetParser/AArch64TargetParser.cpp
index 50c9a565e7ae25..49ac7a75772b55 100644
--- a/llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -281,6 +281,9 @@ void AArch64::ExtensionSet::disable(ArchExtKind E) {
if (E == AEK_SVE2AES)
disable(AEK_SVEAES);
+ if (E == AEK_SVE2BITPERM)
+ disable(AEK_SVEBITPERM);
+
if (!Enabled.test(E))
return;
diff --git a/llvm/test/MC/AArch64/SVE2/bdep-diagnostics.s
b/llvm/test/MC/AArch64/SVE2/bdep-diagnostics.s
index 08a589e1f963f2..9e40830882c87b 100644
--- a/llvm/test/MC/AArch64/SVE2/bdep-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE2/bdep-diagnostics.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-bitperm 2>&1
< %s| FileCheck %s
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2,+sve-bitperm
2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
diff --git a/llvm/test/MC/AArch64/SVE2/bdep.s b/llvm/test/MC/AArch64/SVE2/bdep.s
index a6ef95d9f26194..bae4ae6bab9520 100644
--- a/llvm/test/MC/AArch64/SVE2/bdep.s
+++ b/llvm/test/MC/AArch64/SVE2/bdep.s
@@ -12,23 +12,23 @@
bdep z0.b, z1.b, z31.b
// CHECK-INST: bdep z0.b, z1.b, z31.b
// CHECK-ENCODING: [0x20,0xb4,0x1f,0x45]
-// CHECK-ERROR: instruction requires: sve2-bitperm
+// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 451fb420 <unknown>
bdep z0.h, z1.h, z31.h
// CHECK-INST: bdep z0.h, z1.h, z31.h
// CHECK-ENCODING: [0x20,0xb4,0x5f,0x45]
-// CHECK-ERROR: instruction requires: sve2-bitperm
+// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 455fb420 <unknown>
bdep z0.s, z1.s, z31.s
// CHECK-INST: bdep z0.s, z1.s, z31.s
// CHECK-ENCODING: [0x20,0xb4,0x9f,0x45]
-// CHECK-ERROR: instruction requires: sve2-bitperm
+// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 459fb420 <unknown>
bdep z0.d, z1.d, z31.d
// CHECK-INST: bdep z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xb4,0xdf,0x45]
-// CHECK-ERROR: instruction requires: sve2-bitperm
+// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 45dfb420 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2/bext.s b/llvm/test/MC/AArch64/SVE2/bext.s
index 43272205ab897e..7ae18d6ed25333 100644
--- a/llvm/test/MC/AArch64/SVE2/bext.s
+++ b/llvm/test/MC/AArch64/SVE2/bext.s
@@ -12,23 +12,23 @@
bext z0.b, z1.b, z31.b
// CHECK-INST: bext z0.b, z1.b, z31.b
// CHECK-ENCODING: [0x20,0xb0,0x1f,0x45]
-// CHECK-ERROR: instruction requires: sve2-bitperm
+// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 451fb020 <unknown>
bext z0.h, z1.h, z31.h
// CHECK-INST: bext z0.h, z1.h, z31.h
// CHECK-ENCODING: [0x20,0xb0,0x5f,0x45]
-// CHECK-ERROR: instruction requires: sve2-bitperm
+// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 455fb020 <unknown>
bext z0.s, z1.s, z31.s
// CHECK-INST: bext z0.s, z1.s, z31.s
// CHECK-ENCODING: [0x20,0xb0,0x9f,0x45]
-// CHECK-ERROR: instruction requires: sve2-bitperm
+// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 459fb020 <unknown>
bext z0.d, z1.d, z31.d
// CHECK-INST: bext z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xb0,0xdf,0x45]
-// CHECK-ERROR: instruction requires: sve2-bitperm
+// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 45dfb020 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2/bgrp.s b/llvm/test/MC/AArch64/SVE2/bgrp.s
index fb96946dc3c531..3c37f21ac0b8b7 100644
--- a/llvm/test/MC/AArch64/SVE2/bgrp.s
+++ b/llvm/test/MC/AArch64/SVE2/bgrp.s
@@ -12,23 +12,23 @@
bgrp z0.b, z1.b, z31.b
// CHECK-INST: bgrp z0.b, z1.b, z31.b
// CHECK-ENCODING: [0x20,0xb8,0x1f,0x45]
-// CHECK-ERROR: instruction requires: sve2-bitperm
+// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 451fb820 <unknown>
bgrp z0.h, z1.h, z31.h
// CHECK-INST: bgrp z0.h, z1.h, z31.h
// CHECK-ENCODING: [0x20,0xb8,0x5f,0x45]
-// CHECK-ERROR: instruction requires: sve2-bitperm
+// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 455fb820 <unknown>
bgrp z0.s, z1.s, z31.s
// CHECK-INST: bgrp z0.s, z1.s, z31.s
// CHECK-ENCODING: [0x20,0xb8,0x9f,0x45]
-// CHECK-ERROR: instruction requires: sve2-bitperm
+// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 459fb820 <unknown>
bgrp z0.d, z1.d, z31.d
// CHECK-INST: bgrp z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xb8,0xdf,0x45]
-// CHECK-ERROR: instruction requires: sve2-bitperm
+// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 45dfb820 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
b/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
index 090d8af85825a3..2cfce3b232ffcd 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
@@ -29,10 +29,16 @@ rax1 z0.d, z0.d, z0.d
// CHECK: error: instruction requires: sve2-sha3
// CHECK-NEXT: rax1 z0.d, z0.d, z0.d
-.arch armv9-a+sve2-bitperm
-.arch armv9-a+nosve2-bitperm
+.arch armv9-a+ssve-bitperm
+.arch armv9-a+nossve-bitperm
bgrp z21.s, z10.s, z21.s
-// CHECK: error: instruction requires: sve2-bitperm
+// CHECK: error: instruction requires: sve-bitperm
+// CHECK-NEXT: bgrp z21.s, z10.s, z21.s
+
+.arch armv9-a+sve2+sve-bitperm
+.arch armv9-a+sve2+nosve-bitperm
+bgrp z21.s, z10.s, z21.s
+// CHECK: error: instruction requires: sve-bitperm
// CHECK-NEXT: bgrp z21.s, z10.s, z21.s
.arch armv9-a+f8f16mm
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch.s
b/llvm/test/MC/AArch64/SVE2/directive-arch.s
index 1319a8a186971c..203541a09ad373 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch.s
@@ -20,7 +20,11 @@ sm4e z0.s, z0.s, z0.s
rax1 z0.d, z0.d, z0.d
// CHECK: rax1 z0.d, z0.d, z0.d
-.arch armv9-a+sve2-bitperm
+.arch armv9-a+sve2+sve-bitperm
+bgrp z21.s, z10.s, z21.s
+// CHECK: bgrp z21.s, z10.s, z21.s
+
+.arch armv9-a+ssve-bitperm
bgrp z21.s, z10.s, z21.s
// CHECK: bgrp z21.s, z10.s, z21.s
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
b/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
index 2eb22ebf7428c5..4e3ad3172b01ab 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
@@ -34,7 +34,7 @@ rax1 z0.d, z0.d, z0.d
.arch_extension sve2-bitperm
.arch_extension nosve2-bitperm
bgrp z21.s, z10.s, z21.s
-// CHECK: error: instruction requires: sve2-bitperm
+// CHECK: error: instruction requires: sve-bitperm
// CHECK-NEXT: bgrp z21.s, z10.s, z21.s
.arch_extension f8f16mm
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
b/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
index ce56127ca93b1c..e45e1f9881422e 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
@@ -20,7 +20,7 @@ sm4e z0.s, z0.s, z0.s
rax1 z0.d, z0.d, z0.d
// CHECK: rax1 z0.d, z0.d, z0.d
-.arch_extension sve2-bitperm
+.arch_extension ssve-bitperm
bgrp z21.s, z10.s, z21.s
// CHECK: bgrp z21.s, z10.s, z21.s
diff --git a/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
b/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
index 461b9298df6219..a50b990949424b 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
@@ -29,10 +29,16 @@ rax1 z0.d, z0.d, z0.d
// CHECK: error: instruction requires: sve2-sha3
// CHECK-NEXT: rax1 z0.d, z0.d, z0.d
-.cpu generic+sve2-bitperm
-.cpu generic+nosve2-bitperm
+.cpu generic+sve2+sve-bitperm
+.cpu generic+sve2+nosve-bitperm
bgrp z21.s, z10.s, z21.s
-// CHECK: error: instruction requires: sve2-bitperm
+// CHECK: error: instruction requires: sve-bitperm
+// CHECK-NEXT: bgrp z21.s, z10.s, z21.s
+
+.cpu generic+ssve-bitperm
+.cpu generic+nossve-bitperm
+bgrp z21.s, z10.s, z21.s
+// CHECK: error: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-NEXT: bgrp z21.s, z10.s, z21.s
.cpu generic+sve2+f8f16mm
diff --git a/llvm/test/MC/AArch64/SVE2/directive-cpu.s
b/llvm/test/MC/AArch64/SVE2/directive-cpu.s
index c54a3a9f272c3d..0d873dd9b53f1c 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-cpu.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-cpu.s
@@ -20,7 +20,11 @@ sm4e z0.s, z0.s, z0.s
rax1 z0.d, z0.d, z0.d
// CHECK: rax1 z0.d, z0.d, z0.d
-.cpu generic+sve2-bitperm
+.cpu generic+sve2+sve-bitperm
+bgrp z21.s, z10.s, z21.s
+// CHECK: bgrp z21.s, z10.s, z21.s
+
+.cpu generic+ssve-bitperm
bgrp z21.s, z10.s, z21.s
// CHECK: bgrp z21.s, z10.s, z21.s
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp
b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 1f69190e4bec53..90f1e5fb1814f5 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1343,7 +1343,9 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_FPRCVT, AArch64::AEK_CMPBR,
AArch64::AEK_LSUI, AArch64::AEK_OCCMO,
AArch64::AEK_PCDPHINT, AArch64::AEK_POPS,
- AArch64::AEK_SVEAES};
+ AArch64::AEK_SVEAES, AArch64::AEK_SVEBITPERM,
+ AArch64::AEK_SSVE_BITPERM,
+ };
std::vector<StringRef> Features;
@@ -1382,7 +1384,9 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
EXPECT_TRUE(llvm::is_contained(Features, "+sve2-aes"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve2-sm4"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve2-sha3"));
+ EXPECT_TRUE(llvm::is_contained(Features, "+sve-bitperm"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve2-bitperm"));
+ EXPECT_TRUE(llvm::is_contained(Features, "+ssve-bitperm"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve-aes2"));
EXPECT_TRUE(llvm::is_contained(Features, "+ssve-aes"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve2p1"));
@@ -1554,6 +1558,8 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
{"sve2-sha3", "nosve2-sha3", "+sve2-sha3", "-sve2-sha3"},
{"sve2p1", "nosve2p1", "+sve2p1", "-sve2p1"},
{"sve2p2", "nosve2p2", "+sve2p2", "-sve2p2"},
+ {"sve-bitperm", "nosve-bitperm", "+sve-bitperm", "-sve-bitperm"},
+ {"ssve-bitperm", "nossve-bitperm", "+ssve-bitperm", "-ssve-bitperm"},
{"sve2-bitperm", "nosve2-bitperm", "+sve2-bitperm", "-sve2-bitperm"},
{"sve-aes2", "nosve-aes2", "+sve-aes2", "-sve-aes2"},
{"ssve-aes", "nossve-aes", "+ssve-aes", "-ssve-aes"},
@@ -1754,13 +1760,13 @@ AArch64ExtensionDependenciesBaseArchTestParams
// Long dependency chains: sve2-bitperm -> sve2 -> sve -> fp16 -> fp
{AArch64::ARMV8A,
- {"nofp", "sve2-bitperm"},
- {"fp-armv8", "fullfp16", "sve", "sve2", "sve2-bitperm"},
+ {"nofp", "sve2", "sve-bitperm"},
+ {"fp-armv8", "fullfp16", "sve", "sve2", "sve-bitperm"},
{}},
{AArch64::ARMV8A,
- {"sve2-bitperm", "nofp16"},
+ {"sve2", "sve-bitperm", "nofp16"},
{"fp-armv8"},
- {"full-fp16", "sve", "sve2", "sve2-bitperm"}},
+ {"full-fp16", "sve", "sve2", "sve-bitperm"}},
// Meaning of +crypto varies with base architecture.
{AArch64::ARMV8A, {"crypto"}, {"aes", "sha2"}, {}},
@@ -1860,12 +1866,9 @@ AArch64ExtensionDependenciesBaseArchTestParams
{AArch64::ARMV8A, {"sve2p1", "nosve2"}, {}, {"sve2", "sve2p1"}},
{AArch64::ARMV8A,
{"nosve2", "sve2-bitperm"},
- {"sve2", "sve2-bitperm"},
+ {"sve2", "sve-bitperm"},
{}},
- {AArch64::ARMV8A,
- {"sve2-bitperm", "nosve2"},
- {},
- {"sve2", "sve2-bitperm"}},
+ {AArch64::ARMV8A, {"sve-bitperm", "nosve2"}, {"sve-bitperm"},
{"sve2"}},
{AArch64::ARMV8A, {"nosve2", "sve2-sha3"}, {"sve2", "sve2-sha3"}, {}},
{AArch64::ARMV8A, {"sve2-sha3", "nosve2"}, {}, {"sve2", "sve2-sha3"}},
{AArch64::ARMV8A, {"nosve2", "sve2-sm4"}, {"sve2", "sve2-sm4"}, {}},
@@ -2015,10 +2018,10 @@ AArch64ExtensionDependenciesBaseCPUTestParams
{}},
{"cortex-a520",
{},
- {"v9.2a", "bf16", "crc", "dotprod", "flagm", "fp-armv8",
- "fullfp16", "fp16fml", "i8mm", "lse", "mte", "pauth",
- "perfmon", "predres", "ras", "rcpc", "rdm", "sb",
- "neon", "ssbs", "sve", "sve2-bitperm", "sve2"},
+ {"v9.2a", "bf16", "crc", "dotprod", "flagm", "fp-armv8",
+ "fullfp16", "fp16fml", "i8mm", "lse", "mte", "pauth",
+ "perfmon", "predres", "ras", "rcpc", "rdm", "sb",
+ "neon", "ssbs", "sve", "sve-bitperm", "sve2"},
{}},
// Negative modifiers
@@ -2033,4 +2036,4 @@ INSTANTIATE_TEST_SUITE_P(
AArch64ExtensionDependenciesBaseCPUTestFixture,
::testing::ValuesIn(AArch64ExtensionDependenciesCPUData));
-} // namespace
\ No newline at end of file
+} // namespace
>From 67dbf75b46a61c1864b3256205b8b57e6c84812d Mon Sep 17 00:00:00 2001
From: Caroline Concatto <caroline.conca...@arm.com>
Date: Sun, 12 Jan 2025 17:13:35 +0000
Subject: [PATCH 2/3] Address review comments
---
clang/test/CodeGen/AArch64/fmv-dependencies.c | 2 +-
llvm/lib/Target/AArch64/AArch64Features.td | 2 +-
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 2 +-
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 2 +-
.../Target/AArch64/AsmParser/AArch64AsmParser.cpp | 3 ++-
llvm/test/MC/AArch64/SVE2/bdep.s | 10 ++++++----
llvm/test/MC/AArch64/SVE2/bext.s | 10 ++++++----
llvm/test/MC/AArch64/SVE2/bgrp.s | 10 ++++++----
.../SVE2/directive-arch_extension-negative.s | 6 ++++++
llvm/unittests/TargetParser/TargetParserTest.cpp | 13 ++++++++++++-
10 files changed, 42 insertions(+), 18 deletions(-)
diff --git a/clang/test/CodeGen/AArch64/fmv-dependencies.c
b/clang/test/CodeGen/AArch64/fmv-dependencies.c
index de727fe10d0c61..8dda3b647fcd09 100644
--- a/clang/test/CodeGen/AArch64/fmv-dependencies.c
+++ b/clang/test/CodeGen/AArch64/fmv-dependencies.c
@@ -192,7 +192,7 @@ int caller() {
// CHECK: attributes #[[sve]] = { {{.*}}
"target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a"
// CHECK: attributes #[[sve2]] = { {{.*}}
"target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+v8a"
// CHECK: attributes #[[sve2_aes]] = { {{.*}}
"target-features"="+aes,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve-aes,+sve2,+sve2-aes,+v8a"
-// CHECK: attributes #[[sve2_bitperm]] = { {{.*}}
"target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve-bitperm,+sve2,+v8a"
+// CHECK: attributes #[[sve2_bitperm]] = { {{.*}}
"target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve-bitperm,+sve2,+sve2-bitperm,+v8a"
// CHECK: attributes #[[sve2_sha3]] = { {{.*}}
"target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sha2,+sha3,+sve,+sve2,+sve2-sha3,+v8a"
// CHECK: attributes #[[sve2_sm4]] = { {{.*}}
"target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sm4,+sve,+sve2,+sve2-sm4,+v8a"
// CHECK: attributes #[[wfxt]] = { {{.*}}
"target-features"="+fp-armv8,+neon,+outline-atomics,+v8a,+wfxt"
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td
b/llvm/lib/Target/AArch64/AArch64Features.td
index 34432d8f37efa5..596479fbfe0daf 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -379,7 +379,7 @@ def FeatureSVE2SHA3 : ExtensionWithMArch<"sve2-sha3",
"SVE2SHA3", "FEAT_SVE_SHA3
def FeatureSVEBitPerm : ExtensionWithMArch<"sve-bitperm", "SVEBitPerm",
"FEAT_SVE_BitPerm", "Enable bit permutation SVE2 instructions">;
-def FeatureSVE2BitPerm : ExtensionWithMArch<"sve2-bitperm", "SVE2BitPerm",
+def FeatureAliasSVE2BitPerm : ExtensionWithMArch<"sve2-bitperm", "SVE2BitPerm",
"", "Shorthand for +sve2+sve-bitperm", [FeatureSVE2, FeatureSVEBitPerm]>;
def FeatureTRBE : Extension<"trbe", "TRBE", "FEAT_TRBE",
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 4414c49b65e572..948701f897855a 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -155,7 +155,7 @@ def HasSVE2SM4 :
Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasS
AssemblerPredicateWithAll<(all_of
FeatureSVE2SM4), "sve2-sm4">;
def HasSVE2SHA3 : Predicate<"Subtarget->isSVEAvailable() &&
Subtarget->hasSVE2SHA3()">,
AssemblerPredicateWithAll<(all_of
FeatureSVE2SHA3), "sve2-sha3">;
-def HasSVEBitPerm : Predicate<"Subtarget->isSVEAvailable() &&
Subtarget->hasSVEBitPerm()">,
+def HasSVEBitPerm : Predicate<"Subtarget->hasSVEBitPerm()">,
AssemblerPredicateWithAll<(all_of
FeatureSVEBitPerm), "sve-bitperm">;
def HasSMEandIsNonStreamingSafe
: Predicate<"Subtarget->hasSME()">,
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index bb17ddaa5e3f5b..22715c61126d1b 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -3951,7 +3951,7 @@ let Predicates = [HasSVEBitPerm,
HasNonStreamingSVE2orSSVE_BitPerm] in {
defm BEXT_ZZZ : sve2_misc_bitwise<0b1100, "bext", int_aarch64_sve_bext_x>;
defm BDEP_ZZZ : sve2_misc_bitwise<0b1101, "bdep", int_aarch64_sve_bdep_x>;
defm BGRP_ZZZ : sve2_misc_bitwise<0b1110, "bgrp", int_aarch64_sve_bgrp_x>;
-} // End HasSVE2BitPerm
+}
let Predicates = [HasSVEAES2, HasNonStreamingSVE2p1orSSVE_AES] in {
// SVE_AES2 multi-vector instructions (x2)
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 51eba029e127df..e8605d27d151ed 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3756,7 +3756,8 @@ static const struct Extension {
{"sve2-sm4", {AArch64::FeatureSVE2SM4}},
{"sve2-sha3", {AArch64::FeatureSVE2SHA3}},
{"sve-bitperm", {AArch64::FeatureSVEBitPerm}},
- {"sve2-bitperm", {AArch64::FeatureSVE2BitPerm,
AArch64::FeatureSVEBitPerm}},
+ {"sve2-bitperm",
+ {AArch64::FeatureAliasSVE2BitPerm, AArch64::FeatureSVEBitPerm}},
{"sve2p1", {AArch64::FeatureSVE2p1}},
{"ls64", {AArch64::FeatureLS64}},
{"xs", {AArch64::FeatureXS}},
diff --git a/llvm/test/MC/AArch64/SVE2/bdep.s b/llvm/test/MC/AArch64/SVE2/bdep.s
index bae4ae6bab9520..44c848d0b3b597 100644
--- a/llvm/test/MC/AArch64/SVE2/bdep.s
+++ b/llvm/test/MC/AArch64/SVE2/bdep.s
@@ -1,12 +1,14 @@
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-bitperm < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2,+sve-bitperm < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+ssve-bitperm < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-bitperm < %s \
-// RUN: | llvm-objdump -d --mattr=+sve2-bitperm - | FileCheck %s
--check-prefix=CHECK-INST
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-bitperm < %s \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2,+sve-bitperm < %s \
+// RUN: | llvm-objdump -d --mattr=+sve2,+sve-bitperm - | FileCheck %s
--check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2,+sve-bitperm < %s \
// RUN: | llvm-objdump -d --mattr=-sve2 - | FileCheck %s
--check-prefix=CHECK-UNKNOWN
bdep z0.b, z1.b, z31.b
diff --git a/llvm/test/MC/AArch64/SVE2/bext.s b/llvm/test/MC/AArch64/SVE2/bext.s
index 7ae18d6ed25333..ea519c22cceb5d 100644
--- a/llvm/test/MC/AArch64/SVE2/bext.s
+++ b/llvm/test/MC/AArch64/SVE2/bext.s
@@ -1,12 +1,14 @@
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-bitperm < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2,+sve-bitperm < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+ssve-bitperm < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-bitperm < %s \
-// RUN: | llvm-objdump -d --mattr=+sve2-bitperm - | FileCheck %s
--check-prefix=CHECK-INST
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-bitperm < %s \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2,+sve-bitperm < %s \
+// RUN: | llvm-objdump -d --mattr=+sve2,+sve-bitperm - | FileCheck %s
--check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2,+sve-bitperm < %s \
// RUN: | llvm-objdump -d --mattr=-sve2 - | FileCheck %s
--check-prefix=CHECK-UNKNOWN
bext z0.b, z1.b, z31.b
diff --git a/llvm/test/MC/AArch64/SVE2/bgrp.s b/llvm/test/MC/AArch64/SVE2/bgrp.s
index 3c37f21ac0b8b7..eb58d135115837 100644
--- a/llvm/test/MC/AArch64/SVE2/bgrp.s
+++ b/llvm/test/MC/AArch64/SVE2/bgrp.s
@@ -1,12 +1,14 @@
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-bitperm < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2,+sve-bitperm < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+ssve-bitperm < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-bitperm < %s \
-// RUN: | llvm-objdump -d --mattr=+sve2-bitperm - | FileCheck %s
--check-prefix=CHECK-INST
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-bitperm < %s \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2,+sve-bitperm < %s \
+// RUN: | llvm-objdump -d --mattr=+sve2,+sve-bitperm - | FileCheck %s
--check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2,+sve-bitperm < %s \
// RUN: | llvm-objdump -d --mattr=-sve2 - | FileCheck %s
--check-prefix=CHECK-UNKNOWN
bgrp z0.b, z1.b, z31.b
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
b/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
index 4e3ad3172b01ab..92477c93591e1f 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
@@ -37,6 +37,12 @@ bgrp z21.s, z10.s, z21.s
// CHECK: error: instruction requires: sve-bitperm
// CHECK-NEXT: bgrp z21.s, z10.s, z21.s
+.arch_extension sve2-bitperm
+.arch_extension nosve2
+bgrp z21.s, z10.s, z21.s
+// CHECK: error: instruction requires: sve2
+// CHECK-NEXT: bgrp z21.s, z10.s, z21.s
+
.arch_extension f8f16mm
.arch_extension nof8f16mm
fmmla z23.h, z13.b, z8.b
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp
b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 90f1e5fb1814f5..8bca4fae7ec401 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1868,7 +1868,18 @@ AArch64ExtensionDependenciesBaseArchTestParams
{"nosve2", "sve2-bitperm"},
{"sve2", "sve-bitperm"},
{}},
- {AArch64::ARMV8A, {"sve-bitperm", "nosve2"}, {"sve-bitperm"},
{"sve2"}},
+ {AArch64::ARMV8A,
+ {"sve2-bitperm", "nosve2"},
+ {"sve"},
+ {"sve-bitperm", "sve2", "sve2-bitperm"}},
+ {AArch64::ARMV8A,
+ {"ssve-bitperm", "nosve-bitperm"},
+ {"sme"},
+ {"ssve-bitperm", "sve-bitperm"}},
+ {AArch64::ARMV8A,
+ {"nosve-bitperm", "ssve-bitperm"},
+ {"sve-bitperm", "sve-bitperm"},
+ {""}},
{AArch64::ARMV8A, {"nosve2", "sve2-sha3"}, {"sve2", "sve2-sha3"}, {}},
{AArch64::ARMV8A, {"sve2-sha3", "nosve2"}, {}, {"sve2", "sve2-sha3"}},
{AArch64::ARMV8A, {"nosve2", "sve2-sm4"}, {"sve2", "sve2-sm4"}, {}},
>From cc78fad50b91dba93ad42e1726fbc29907b1c048 Mon Sep 17 00:00:00 2001
From: Caroline Concatto <caroline.conca...@arm.com>
Date: Mon, 13 Jan 2025 13:27:30 +0000
Subject: [PATCH 3/3] Improve error message in the test
---
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 3 ++-
llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s | 4 ++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index e8605d27d151ed..c37c57590f906f 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3757,7 +3757,8 @@ static const struct Extension {
{"sve2-sha3", {AArch64::FeatureSVE2SHA3}},
{"sve-bitperm", {AArch64::FeatureSVEBitPerm}},
{"sve2-bitperm",
- {AArch64::FeatureAliasSVE2BitPerm, AArch64::FeatureSVEBitPerm}},
+ {AArch64::FeatureAliasSVE2BitPerm, AArch64::FeatureSVEBitPerm,
+ AArch64::FeatureSVE2}},
{"sve2p1", {AArch64::FeatureSVE2p1}},
{"ls64", {AArch64::FeatureLS64}},
{"xs", {AArch64::FeatureXS}},
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
b/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
index 92477c93591e1f..2fab61597576f7 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
@@ -34,13 +34,13 @@ rax1 z0.d, z0.d, z0.d
.arch_extension sve2-bitperm
.arch_extension nosve2-bitperm
bgrp z21.s, z10.s, z21.s
-// CHECK: error: instruction requires: sve-bitperm
+// CHECK: error: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-NEXT: bgrp z21.s, z10.s, z21.s
.arch_extension sve2-bitperm
.arch_extension nosve2
bgrp z21.s, z10.s, z21.s
-// CHECK: error: instruction requires: sve2
+// CHECK: error: instruction requires: sve2 or ssve-bitperm
// CHECK-NEXT: bgrp z21.s, z10.s, z21.s
.arch_extension f8f16mm
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