https://github.com/hchandel created https://github.com/llvm/llvm-project/pull/121752
The Qualcomm uC Xqcicm extension adds 13 conditional move instructions. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. >From 9a4f77a07df6aa926b121b2ac1e9c251fe39b3af Mon Sep 17 00:00:00 2001 From: Harsh Chandel <hchan...@qti.qualcomm.com> Date: Fri, 3 Jan 2025 18:02:09 +0530 Subject: [PATCH 1/2] [RISCV] Add Qualcomm uC Xqcicm (Conditional Move) extension The Qualcomm uC Xqcicm extension adds 13 conditional move instructions. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. Change-Id: I301fffd3223b48e32658ef85d602dbb9d50a2a57 --- .../Driver/print-supported-extensions-riscv.c | 1 + llvm/docs/RISCVUsage.rst | 3 + llvm/docs/ReleaseNotes.md | 2 + .../RISCV/Disassembler/RISCVDisassembler.cpp | 5 + llvm/lib/Target/RISCV/RISCVFeatures.td | 8 + llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 63 ++++++++ llvm/lib/TargetParser/RISCVISAInfo.cpp | 4 +- llvm/test/CodeGen/RISCV/attributes.ll | 2 + llvm/test/MC/RISCV/xqcicm-invalid.s | 152 ++++++++++++++++++ llvm/test/MC/RISCV/xqcicm-valid.s | 123 ++++++++++++++ .../TargetParser/RISCVISAInfoTest.cpp | 5 +- 11 files changed, 364 insertions(+), 4 deletions(-) create mode 100644 llvm/test/MC/RISCV/xqcicm-invalid.s create mode 100644 llvm/test/MC/RISCV/xqcicm-valid.s diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 395501eb85ccc3..7f2cfa9b16ad36 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -191,6 +191,7 @@ // CHECK-NEXT: xqcia 0.2 'Xqcia' (Qualcomm uC Arithmetic Extension) // CHECK-NEXT: xqciac 0.2 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension) // CHECK-NEXT: xqcicli 0.2 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension) +// CHECK-NEXT: xqcicm 0.2 'Xqcicm' (Qualcomm uC Conditional Move Extension) // CHECK-NEXT: xqcics 0.2 'Xqcics' (Qualcomm uC Conditional Select Extension) // CHECK-NEXT: xqcicsr 0.2 'Xqcicsr' (Qualcomm uC CSR Extension) // CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index eaaad6c5168189..c26398704654c2 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -435,6 +435,9 @@ The current vendor extensions supported are: ``experimental-Xqcicli`` LLVM implements `version 0.2 of the Qualcomm uC Conditional Load Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. +``experimental-Xqcicm`` + LLVM implements `version 0.2 of the Qualcomm uC Conditional Move extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. + ``experimental-Xqcics`` LLVM implements `version 0.2 of the Qualcomm uC Conditional Select extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index be62a7e8696b4c..3d84dd893fb65e 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -232,6 +232,8 @@ Changes to the RISC-V Backend extension. * Adds experimental assembler support for the Qualcomm uC 'Xqcicli` (Conditional Load Immediate) extension. +* Adds experimental assembler support for the Qualcomm uC 'Xqcicm` (Conditonal Move) + extension. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 30122831767f61..a490910154eb4d 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -698,6 +698,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size, TRY_TO_DECODE_FEATURE( RISCV::FeatureVendorXqcicli, DecoderTableXqcicli32, "Qualcomm uC Conditional Load Immediate custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcicm, DecoderTableXqcicm32, + "Qualcomm uC Conditional Move custom opcode table"); TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table"); return MCDisassembler::Fail; @@ -727,6 +729,9 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size, TRY_TO_DECODE_FEATURE( RISCV::FeatureVendorXqciac, DecoderTableXqciac16, "Qualcomm uC Load-Store Address Calculation custom 16bit opcode table"); + TRY_TO_DECODE_FEATURE( + RISCV::FeatureVendorXqcicm, DecoderTableXqcicm16, + "Qualcomm uC Conditional Move custom 16bit opcode table"); TRY_TO_DECODE_AND_ADD_SP(STI.hasFeature(RISCV::FeatureVendorXwchc), DecoderTableXwchc16, "WCH QingKe XW custom opcode table"); diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 3885b95a8937a8..3b4426223d03a9 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1290,6 +1290,14 @@ def HasVendorXqcicli AssemblerPredicate<(all_of FeatureVendorXqcicli), "'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)">; +def FeatureVendorXqcicm + : RISCVExperimentalExtension<0, 2, "Qualcomm uC Conditional Move Extension", + [FeatureStdExtZca]>; +def HasVendorXqcicm + : Predicate<"Subtarget->hasVendorXqcicm()">, + AssemblerPredicate<(all_of FeatureVendorXqcicm), + "'Xqcicm' (Qualcomm uC Conditional Move Extension)">; + //===----------------------------------------------------------------------===// // LLVM specific features and extensions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td index 5e6722cb4995e2..039935deae10c8 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td @@ -150,6 +150,33 @@ class QCILICC<bits<3> funct3, bits<2> funct2, DAGOperand InTyRs2, string opcodes let Inst{31-25} = {simm, funct2}; } +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in +class QCIMVCC<bits<3> funct3, string opcodestr> + : RVInstR4<0b00, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd), + (ins GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs3), + opcodestr, "$rd, $rs1, $rs2, $rs3"> { +} + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in +class QCIMVCCI<bits<3> funct3, string opcodestr> + : RVInstR4<0b10, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd), + (ins GPRNoX0:$rs1, simm5:$imm, GPRNoX0:$rs3), + opcodestr, "$rd, $rs1, $imm, $rs3"> { + bits<5> imm; + + let rs2 = imm; +} + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in +class QCIMVCCUI<bits<3> funct3, string opcodestr> + : RVInstR4<0b10, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd), + (ins GPRNoX0:$rs1, uimm5:$imm, GPRNoX0:$rs3), + opcodestr, "$rd, $rs1, $imm, $rs3"> { + bits<5> imm; + + let rs2 = imm; +} + //===----------------------------------------------------------------------===// // Instructions //===----------------------------------------------------------------------===// @@ -270,6 +297,42 @@ let Predicates = [HasVendorXqcicli, IsRV32], DecoderNamespace = "Xqcicli" in { def QC_LIGEUI : QCILICC<0b111, 0b11, uimm5, "qc.ligeui">; } // Predicates = [HasVendorXqcicli, IsRV32], DecoderNamespace = "Xqcicli" +let Predicates = [HasVendorXqcicm, IsRV32], DecoderNamespace = "Xqcicm" in { +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in + def QC_C_MVEQZ : RVInst16CL<0b101, 0b10, (outs GPRC:$rd_wb), + (ins GPRC:$rd, GPRC:$rs1), + "qc.c.mveqz", "$rd, $rs1"> { + let Constraints = "$rd = $rd_wb"; + + let Inst{12-10} = 0b011; + let Inst{6-5} = 0b00; + } + + def QC_MVEQ : QCIMVCC<0b000, "qc.mveq">; + + def QC_MVNE : QCIMVCC<0b001, "qc.mvne">; + + def QC_MVLT : QCIMVCC<0b100, "qc.mvlt">; + + def QC_MVGE : QCIMVCC<0b101, "qc.mvge">; + + def QC_MVLTU : QCIMVCC<0b110, "qc.mvltu">; + + def QC_MVGEU : QCIMVCC<0b111, "qc.mvgeu">; + + def QC_MVEQI : QCIMVCCI <0b000, "qc.mveqi">; + + def QC_MVNEI : QCIMVCCI <0b001, "qc.mvnei">; + + def QC_MVLTI : QCIMVCCI <0b100, "qc.mvlti">; + + def QC_MVGEI : QCIMVCCI <0b101, "qc.mvgei">; + + def QC_MVLTUI : QCIMVCCUI<0b110, "qc.mvltui">; + + def QC_MVGEUI : QCIMVCCUI<0b111, "qc.mvgeui">; +} // Predicates = [HasVendorXqcicm, IsRV32], DecoderNamespace = "Xqcicm" + //===----------------------------------------------------------------------===// // Aliases //===----------------------------------------------------------------------===// diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp index 4f403e9fb6f574..d6e1eac0d85af4 100644 --- a/llvm/lib/TargetParser/RISCVISAInfo.cpp +++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp @@ -742,8 +742,8 @@ Error RISCVISAInfo::checkDependency() { bool HasZvl = MinVLen != 0; bool HasZcmt = Exts.count("zcmt") != 0; static constexpr StringLiteral XqciExts[] = { - {"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcics"}, - {"xqcicsr"}, {"xqcilsm"}, {"xqcisls"}}; + {"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcicm"}, + {"xqcics"}, {"xqcicsr"}, {"xqcilsm"}, {"xqcisls"}}; if (HasI && HasE) return getIncompatibleError("i", "e"); diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index bcf945470d85b3..b4634dafd50f78 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -84,6 +84,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcia %s -o - | FileCheck --check-prefix=RV32XQCIA %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqciac %s -o - | FileCheck --check-prefix=RV32XQCIAC %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicli %s -o - | FileCheck --check-prefix=RV32XQCICLI %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm %s -o - | FileCheck --check-prefix=RV32XQCICM %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics %s -o - | FileCheck --check-prefix=RV32XQCICS %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicsr %s -o - | FileCheck --check-prefix=RV32XQCICSR %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilsm %s -o - | FileCheck --check-prefix=RV32XQCILSM %s @@ -395,6 +396,7 @@ ; RV32XQCIA: .attribute 5, "rv32i2p1_xqcia0p2" ; RV32XQCIAC: .attribute 5, "rv32i2p1_zca1p0_xqciac0p2" ; RV32XQCICLI: .attribute 5, "rv32i2p1_xqcicli0p2" +; RV32XQCICM: .attribute 5, "rv32i2p1_zca1p0_xqcicm0p2" ; RV32XQCICS: .attribute 5, "rv32i2p1_xqcics0p2" ; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p2" ; RV32XQCILSM: .attribute 5, "rv32i2p1_xqcilsm0p2" diff --git a/llvm/test/MC/RISCV/xqcicm-invalid.s b/llvm/test/MC/RISCV/xqcicm-invalid.s new file mode 100644 index 00000000000000..8b37ed4edeb006 --- /dev/null +++ b/llvm/test/MC/RISCV/xqcicm-invalid.s @@ -0,0 +1,152 @@ +# Xqcicm - Qualcomm uC Conditional Move Extension +# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcicm < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-IMM %s +# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcicm < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-EXT %s + +# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction +qc.c.mveqz 9, x10 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.c.mveqz x9 + +# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension) +qc.c.mveqz x9, x10 + + +# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction +qc.mveq 9, x10, x11, x12 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.mveq x9 + +# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension) +qc.mveq x9, x10, x11, x12 + + +# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction +qc.mvge 9, x10, x11, x12 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.mvge x9 + +# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension) +qc.mvge x9, x10, x11, x12 + + +# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +qc.mvgeu 9, x10, x11, x12 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.mvgeu x9 + +# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension) +qc.mvgeu x9, x10, x11, x12 + + +# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction +qc.mvlt 9, x10, x11, x12 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.mvlt x9 + +# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension) +qc.mvlt x9, x10, x11, x12 + + +# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +qc.mvltu 9, x10, x11, x12 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.mvltu x9 + +# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension) +qc.mvltu x9, x10, x11, x12 + + +# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction +qc.mvne 9, x10, x11, x12 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.mvne x9 + +# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension) +qc.mvne x9, x10, x11, x12 + + +# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +qc.mveqi 9, x10, 5, x12 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.mveqi x9 + +# CHECK-IMM: :[[@LINE+1]]:19: error: immediate must be an integer in the range [-16, 15] +qc.mveqi x9, x10, 17, x12 + +# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension) +qc.mveqi x9, x10, 5, x12 + + +# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +qc.mvgei 9, x10, 5, x12 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.mvgei x9 + +# CHECK-IMM: :[[@LINE+1]]:19: error: immediate must be an integer in the range [-16, 15] +qc.mvgei x9, x10, 17, x12 + +# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension) +qc.mvgei x9, x10, 5, x12 + + +# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +qc.mvlti 9, x10, 5, x12 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.mvlti x9 + +# CHECK-IMM: :[[@LINE+1]]:19: error: immediate must be an integer in the range [-16, 15] +qc.mvlti x9, x10, 17, x12 + +# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension) +qc.mvlti x9, x10, 5, x12 + + +# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +qc.mvnei 9, x10, 5, x12 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.mvnei x9 + +# CHECK-IMM: :[[@LINE+1]]:19: error: immediate must be an integer in the range [-16, 15] +qc.mvnei x9, x10, 17, x12 + +# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension) +qc.mvnei x9, x10, 5, x12 + + +# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction +qc.mvltui 9, x10, 5, x12 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.mvltui x9 + +# CHECK-IMM: :[[@LINE+1]]:20: error: immediate must be an integer in the range [0, 31] +qc.mvltui x9, x10, 37, x12 + +# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension) +qc.mvltui x9, x10, 5, x12 + + +# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction +qc.mvgeui 9, x10, 5, x12 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.mvgeui x9 + +# CHECK-IMM: :[[@LINE+1]]:20: error: immediate must be an integer in the range [0, 31] +qc.mvgeui x9, x10, 37, x12 + +# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension) +qc.mvgeui x9, x10, 5, x12 diff --git a/llvm/test/MC/RISCV/xqcicm-valid.s b/llvm/test/MC/RISCV/xqcicm-valid.s new file mode 100644 index 00000000000000..7d0050b6dafa81 --- /dev/null +++ b/llvm/test/MC/RISCV/xqcicm-valid.s @@ -0,0 +1,123 @@ +# Xqcicm - Qualcomm uC Conditional Move Extension +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicm -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicm < %s \ +# RUN: | llvm-objdump --mattr=+experimental-xqcicm -M no-aliases --no-print-imm-hex -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicm -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicm < %s \ +# RUN: | llvm-objdump --mattr=+experimental-xqcicm --no-print-imm-hex -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s + +# CHECK-INST: qc.c.mveqz s1, a0 +# CHECK-ENC: encoding: [0x06,0xad] +qc.c.mveqz x9, x10 + + +# CHECK-INST: qc.mveq s1, a0, a1, a2 +# CHECK-ENC: encoding: [0xdb,0x04,0xb5,0x60] +qc.mveq x9, x10, x11, x12 + + +# CHECK-INST: qc.mvge s1, a0, a1, a2 +# CHECK-ENC: encoding: [0xdb,0x54,0xb5,0x60] +qc.mvge x9, x10, x11, x12 + + +# CHECK-INST: qc.mvgeu s1, a0, a1, a2 +# CHECK-ENC: encoding: [0xdb,0x74,0xb5,0x60] +qc.mvgeu x9, x10, x11, x12 + + +# CHECK-INST: qc.mvlt s1, a0, a1, a2 +# CHECK-ENC: encoding: [0xdb,0x44,0xb5,0x60] +qc.mvlt x9, x10, x11, x12 + + +# CHECK-INST: qc.mvltu s1, a0, a1, a2 +# CHECK-ENC: encoding: [0xdb,0x64,0xb5,0x60] +qc.mvltu x9, x10, x11, x12 + + +# CHECK-INST: qc.mvne s1, a0, a1, a2 +# CHECK-ENC: encoding: [0xdb,0x14,0xb5,0x60] +qc.mvne x9, x10, x11, x12 + + +# CHECK-INST: qc.mveqi s1, a0, 5, a2 +# CHECK-ENC: encoding: [0xdb,0x04,0x55,0x64] +qc.mveqi x9, x10, 5, x12 + +# CHECK-INST: qc.mveqi s1, a0, -16, a2 +# CHECK-ENC: encoding: [0xdb,0x04,0x05,0x65] +qc.mveqi x9, x10, -16, x12 + +# CHECK-INST: qc.mveqi s1, a0, 15, a2 +# CHECK-ENC: encoding: [0xdb,0x04,0xf5,0x64] +qc.mveqi x9, x10, 15, x12 + + +# CHECK-INST: qc.mvgei s1, a0, 5, a2 +# CHECK-ENC: encoding: [0xdb,0x54,0x55,0x64] +qc.mvgei x9, x10, 5, x12 + +# CHECK-INST: qc.mvgei s1, a0, -16, a2 +# CHECK-ENC: encoding: [0xdb,0x54,0x05,0x65] +qc.mvgei x9, x10, -16, x12 + +# CHECK-INST: qc.mvgei s1, a0, 15, a2 +# CHECK-ENC: encoding: [0xdb,0x54,0xf5,0x64] +qc.mvgei x9, x10, 15, x12 + + +# CHECK-INST: qc.mvlti s1, a0, 5, a2 +# CHECK-ENC: encoding: [0xdb,0x44,0x55,0x64] +qc.mvlti x9, x10, 5, x12 + +# CHECK-INST: qc.mvlti s1, a0, -16, a2 +# CHECK-ENC: encoding: [0xdb,0x44,0x05,0x65] +qc.mvlti x9, x10, -16, x12 + +# CHECK-INST: qc.mvlti s1, a0, 15, a2 +# CHECK-ENC: encoding: [0xdb,0x44,0xf5,0x64] +qc.mvlti x9, x10, 15, x12 + + +# CHECK-INST: qc.mvnei s1, a0, 5, a2 +# CHECK-ENC: encoding: [0xdb,0x14,0x55,0x64] +qc.mvnei x9, x10, 5, x12 + +# CHECK-INST: qc.mvnei s1, a0, -16, a2 +# CHECK-ENC: encoding: [0xdb,0x14,0x05,0x65] +qc.mvnei x9, x10, -16, x12 + +# CHECK-INST: qc.mvnei s1, a0, 15, a2 +# CHECK-ENC: encoding: [0xdb,0x14,0xf5,0x64] +qc.mvnei x9, x10, 15, x12 + + +# CHECK-INST: qc.mvltui s1, a0, 5, a2 +# CHECK-ENC: encoding: [0xdb,0x64,0x55,0x64] +qc.mvltui x9, x10, 5, x12 + +# CHECK-INST: qc.mvltui s1, a0, 0, a2 +# CHECK-ENC: encoding: [0xdb,0x64,0x05,0x64] +qc.mvltui x9, x10, 0, x12 + +# CHECK-INST: qc.mvltui s1, a0, 31, a2 +# CHECK-ENC: encoding: [0xdb,0x64,0xf5,0x65] +qc.mvltui x9, x10, 31, x12 + + +# CHECK-INST: qc.mvgeui s1, a0, 5, a2 +# CHECK-ENC: encoding: [0xdb,0x74,0x55,0x64] +qc.mvgeui x9, x10, 5, x12 + +# CHECK-INST: qc.mvgeui s1, a0, 0, a2 +# CHECK-ENC: encoding: [0xdb,0x74,0x05,0x64] +qc.mvgeui x9, x10, 0, x12 + +# CHECK-INST: qc.mvgeui s1, a0, 31, a2 +# CHECK-ENC: encoding: [0xdb,0x74,0xf5,0x65] +qc.mvgeui x9, x10, 31, x12 diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index f631f26cf482eb..b825df81a1e875 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -655,8 +655,8 @@ TEST(ParseArchString, RejectsConflictingExtensions) { for (StringRef Input : {"rv64i_xqcisls0p2", "rv64i_xqcia0p2", "rv64i_xqciac0p2", - "rv64i_xqcicsr0p2", "rv64i_xqcilsm0p2", "rv64i_xqcics0p2", - "rv64i_xqcicli0p2"}) { + "rv64i_xqcicsr0p2", "rv64i_xqcilsm0p2", "rv64i_xqcicm0p2", + "rv64i_xqcics0p2", "rv64i_xqcicli0p2"}) { EXPECT_THAT( toString(RISCVISAInfo::parseArchString(Input, true).takeError()), ::testing::EndsWith(" is only supported for 'rv32'")); @@ -1116,6 +1116,7 @@ Experimental extensions xqcia 0.2 xqciac 0.2 xqcicli 0.2 + xqcicm 0.2 xqcics 0.2 xqcicsr 0.2 xqcilsm 0.2 >From 84c4f797f7656a819040a114d2d40b0942d8ff59 Mon Sep 17 00:00:00 2001 From: Harsh Chandel <hchan...@qti.qualcomm.com> Date: Mon, 6 Jan 2025 14:21:33 +0530 Subject: [PATCH 2/2] Additional Changes Change-Id: If201b1c194b91da0321e3cbe2d3288f1069a06e7 --- llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 36 +++++---------------- 1 file changed, 8 insertions(+), 28 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td index 039935deae10c8..d4a9c5832b436c 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td @@ -158,25 +158,15 @@ class QCIMVCC<bits<3> funct3, string opcodestr> } let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in -class QCIMVCCI<bits<3> funct3, string opcodestr> +class QCIMVCCI<bits<3> funct3, string opcodestr, DAGOperand immType> : RVInstR4<0b10, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd), - (ins GPRNoX0:$rs1, simm5:$imm, GPRNoX0:$rs3), + (ins GPRNoX0:$rs1, immType:$imm, GPRNoX0:$rs3), opcodestr, "$rd, $rs1, $imm, $rs3"> { bits<5> imm; let rs2 = imm; } -let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in -class QCIMVCCUI<bits<3> funct3, string opcodestr> - : RVInstR4<0b10, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd), - (ins GPRNoX0:$rs1, uimm5:$imm, GPRNoX0:$rs3), - opcodestr, "$rd, $rs1, $imm, $rs3"> { - bits<5> imm; - - let rs2 = imm; -} - //===----------------------------------------------------------------------===// // Instructions //===----------------------------------------------------------------------===// @@ -309,28 +299,18 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in } def QC_MVEQ : QCIMVCC<0b000, "qc.mveq">; - def QC_MVNE : QCIMVCC<0b001, "qc.mvne">; - def QC_MVLT : QCIMVCC<0b100, "qc.mvlt">; - def QC_MVGE : QCIMVCC<0b101, "qc.mvge">; - def QC_MVLTU : QCIMVCC<0b110, "qc.mvltu">; - def QC_MVGEU : QCIMVCC<0b111, "qc.mvgeu">; - def QC_MVEQI : QCIMVCCI <0b000, "qc.mveqi">; - - def QC_MVNEI : QCIMVCCI <0b001, "qc.mvnei">; - - def QC_MVLTI : QCIMVCCI <0b100, "qc.mvlti">; - - def QC_MVGEI : QCIMVCCI <0b101, "qc.mvgei">; - - def QC_MVLTUI : QCIMVCCUI<0b110, "qc.mvltui">; - - def QC_MVGEUI : QCIMVCCUI<0b111, "qc.mvgeui">; + def QC_MVEQI : QCIMVCCI<0b000, "qc.mveqi", simm5>; + def QC_MVNEI : QCIMVCCI<0b001, "qc.mvnei", simm5>; + def QC_MVLTI : QCIMVCCI<0b100, "qc.mvlti", simm5>; + def QC_MVGEI : QCIMVCCI<0b101, "qc.mvgei", simm5>; + def QC_MVLTUI : QCIMVCCI<0b110, "qc.mvltui", uimm5>; + def QC_MVGEUI : QCIMVCCI<0b111, "qc.mvgeui", uimm5>; } // Predicates = [HasVendorXqcicm, IsRV32], DecoderNamespace = "Xqcicm" //===----------------------------------------------------------------------===// _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
