================
@@ -184,6 +191,37 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
} // Predicates = [HasVendorXqcia, IsRV32], DecoderNamespace = "Xqcia"
+let Predicates = [HasVendorXqciac, IsRV32], DecoderNamespace = "Xqciac" in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+ def QC_C_MULADDI : RVInst16CL<0b001, 0b10, (outs GPRC:$rd_wb),
+ (ins GPRC:$rd, GPRC:$rs1, uimm5:$uimm),
+ "qc.c.muladdi", "$rd, $rs1, $uimm"> {
+ let Constraints = "$rd = $rd_wb";
+ bits<5> uimm;
+
+ let Inst{12-10} = uimm{3-1};
+ let Inst{6} = uimm{0};
+ let Inst{5} = uimm{4};
+ }
----------------
svs-quic wrote:
Fair enough. However, the current implementation of the CompressPat assumes
that there are no tied operands in the source dag which is not true for the
case of `qc.muladdi`. As a result I'm running into errors in `verifyDagOpCount`
from `CompressInstEmitter.cpp` while writing these patterns. We will need to
change this behaviour before we can write compressed patterns. I am happy to
work on these changes.
Can we merge this patch in its current state and re-visit the compress pattern
once we have fixed the above issue?
```
// Source instructions are non compressed instructions and don't have tied
// operands.
if (IsSource)
PrintFatalError(Inst.TheDef->getLoc(),
"Input operands for Inst '" + Inst.TheDef->getName() +
"' and input Dag operand count mismatch");
```
https://github.com/llvm/llvm-project/pull/121037
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