https://github.com/djtodoro created https://github.com/llvm/llvm-project/pull/119882
The P8700 is a high-performance processor from MIPS designed to meet the demands of modern workloads, offering exceptional scalability and efficiency. It builds on MIPS's established architectural strengths while introducing enhancements that set it apart. For more details, you can check out the official product page here: https://mips.com/products/hardware/p8700/. Scheduling model will be added in a separate commit/PR. >From 6e17be47f6a36f417547d9bff2f31b8c421ee03b Mon Sep 17 00:00:00 2001 From: Djordje Todorovic <djordje.todoro...@htecgroup.com> Date: Mon, 9 Dec 2024 13:01:11 +0100 Subject: [PATCH] [RISCV] Add MIPS P8700 processor The P8700 is a high-performance processor from MIPS designed to meet the demands of modern workloads, offering exceptional scalability and efficiency. It builds on MIPS's established architectural strengths while introducing enhancements that set it apart. For more details, you can check out the official product page here: https://mips.com/products/hardware/p8700/. Scheduling model will be added in a separate commit/PR. --- clang/test/Driver/riscv-cpus.c | 17 +++++++++++++++++ clang/test/Misc/target-invalid-cpu-note/riscv.c | 2 ++ llvm/docs/ReleaseNotes.md | 1 + llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++++ llvm/lib/Target/RISCV/RISCVProcessors.td | 15 +++++++++++++++ 5 files changed, 39 insertions(+) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 249216612f7ee7..1b09945620f8c3 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -98,6 +98,23 @@ // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=rocket-rv64 | FileCheck -check-prefix=MTUNE-ROCKET64 %s // MTUNE-ROCKET64: "-tune-cpu" "rocket-rv64" +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=mips-p8700 | FileCheck -check-prefix=MTUNE-MIPS-P8700 %s +// MTUNE-MIPS-P8700: "-tune-cpu" "mips-p8700" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=mips-p8700 | FileCheck -check-prefix=MCPU-MIPS-P8700 %s +// MCPU-MIPS-P8700: "-target-cpu" "mips-p8700" +// MCPU-MIPS-P8700-SAME: "-target-feature" "+m" +// MCPU-MIPS-P8700-SAME: "-target-feature" "+a" +// MCPU-MIPS-P8700-SAME: "-target-feature" "+f" +// MCPU-MIPS-P8700-SAME: "-target-feature" "+d" +// MCPU-MIPS-P8700-SAME: "-target-feature" "+c" +// MCPU-MIPS-P8700-SAME: "-target-feature" "+zicsr" +// MCPU-MIPS-P8700-SAME: "-target-feature" "+zifencei" +// MCPU-MIPS-P8700-SAME: "-target-feature" "+zaamo" +// MCPU-MIPS-P8700-SAME: "-target-feature" "+zalrsc" +// MCPU-MIPS-P8700-SAME: "-target-feature" "+zba" +// MCPU-MIPS-P8700-SAME: "-target-feature" "+zbb" + // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-base | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-BASE %s // MTUNE-SYNTACORE-SCR1-BASE: "-tune-cpu" "syntacore-scr1-base" diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c index 8c5df5884cd791..fc8536d99cb804 100644 --- a/clang/test/Misc/target-invalid-cpu-note/riscv.c +++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c @@ -25,6 +25,7 @@ // RISCV64: error: unknown target CPU 'not-a-cpu' // RISCV64-NEXT: note: valid target CPU values are: // RISCV64-SAME: {{^}} generic-rv64 +// RISCV64-SAME: {{^}}, mips-p8700 // RISCV64-SAME: {{^}}, rocket-rv64 // RISCV64-SAME: {{^}}, sifive-p450 // RISCV64-SAME: {{^}}, sifive-p470 @@ -72,6 +73,7 @@ // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' // TUNE-RISCV64-NEXT: note: valid target CPU values are: // TUNE-RISCV64-SAME: {{^}} generic-rv64 +// TUNE-RISCV64-SAME: {{^}}, mips-p8700 // TUNE-RISCV64-SAME: {{^}}, rocket-rv64 // TUNE-RISCV64-SAME: {{^}}, sifive-p450 // TUNE-RISCV64-SAME: {{^}}, sifive-p470 diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index a5805e050bfdbe..391568b7a3ad3d 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -195,6 +195,7 @@ Changes to the RISC-V Backend * Added `Smctr`, `Ssctr` and `Svvptc` extensions. * `-mcpu=syntacore-scr7` was added. * `-mcpu=tt-ascalon-d8` was added. +* `-mcpu=mips-p8700` was added. * The `Zacas` extension is no longer marked as experimental. * Added Smdbltrp, Ssdbltrp extensions to -march. * The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 52268c3fa62ccb..3985d83ca075e4 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1477,6 +1477,10 @@ def TuneConditionalCompressedMoveFusion def HasConditionalMoveFusion : Predicate<"Subtarget->hasConditionalMoveFusion()">; def NoConditionalMoveFusion : Predicate<"!Subtarget->hasConditionalMoveFusion()">; +def TuneMIPSP8700 + : SubtargetFeature<"mips-p8700", "RISCVProcFamily", "Others", + "MIPS p8700 processor">; + def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7", "SiFive 7-Series processors">; diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index c4e19c515b155b..7e4bcd07f2fa8a 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -95,6 +95,21 @@ def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64", // to change to the appropriate rv32/rv64 version. def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>, GenericTuneInfo; +def MIPS_P8700 : RISCVProcessorModel<"mips-p8700", + NoSchedModel, + [Feature64Bit, + FeatureStdExtI, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZifencei, + FeatureStdExtZicsr], + [TuneMIPSP8700]>; + def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32", RocketModel, [Feature32Bit, _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
