llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-flang-driver Author: Tarun Prabhu (tarunprabhu) <details> <summary>Changes</summary> The implementation is pretty straightforward. The tests mirror those in clang. --- Patch is 40.87 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/117402.diff 8 Files Affected: - (modified) clang/include/clang/Driver/Options.td (+4-4) - (modified) flang/include/flang/Frontend/FrontendOptions.h (+3) - (modified) flang/lib/Frontend/CompilerInvocation.cpp (+2) - (added) flang/test/Driver/print-supported-extensions-aarch64.f90 (+104) - (added) flang/test/Driver/print-supported-extensions-arm.f90 (+34) - (added) flang/test/Driver/print-supported-extensions-riscv.f90 (+211) - (added) flang/test/Driver/print-supported-extensions.f90 (+10) - (modified) flang/tools/flang-driver/fc1_main.cpp (+46) ``````````diff diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 40fd48761928b3..26be300547ad93 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -5901,15 +5901,15 @@ def print_supported_cpus : Flag<["-", "--"], "print-supported-cpus">, "specified,it will print the supported cpus for the default target)">, MarshallingInfoFlag<FrontendOpts<"PrintSupportedCPUs">>; +def print_supported_extensions : Flag<["-", "--"], "print-supported-extensions">, + HelpText<"Print supported -march extensions (RISC-V, AArch64 and ARM only)">, + MarshallingInfoFlag<FrontendOpts<"PrintSupportedExtensions">>; + def : Flag<["-"], "mcpu=help">, Alias<print_supported_cpus>; def : Flag<["-"], "mtune=help">, Alias<print_supported_cpus>; } // let Visibility = [ClangOption, CC1Option, CLOption, FlangOption, FC1Option] -def print_supported_extensions : Flag<["-", "--"], "print-supported-extensions">, - Visibility<[ClangOption, CC1Option, CLOption]>, - HelpText<"Print supported -march extensions (RISC-V, AArch64 and ARM only)">, - MarshallingInfoFlag<FrontendOpts<"PrintSupportedExtensions">>; def print_enabled_extensions : Flag<["-", "--"], "print-enabled-extensions">, Visibility<[ClangOption, CC1Option, CLOption]>, HelpText<"Print the extensions enabled by the given target and -march/-mcpu options." diff --git a/flang/include/flang/Frontend/FrontendOptions.h b/flang/include/flang/Frontend/FrontendOptions.h index a4cb021e309d4a..fe833e0af587f0 100644 --- a/flang/include/flang/Frontend/FrontendOptions.h +++ b/flang/include/flang/Frontend/FrontendOptions.h @@ -254,6 +254,9 @@ struct FrontendOptions { /// Print the supported cpus for the current target unsigned printSupportedCPUs : 1; + /// Print the supported extensions for the current target + unsigned printSupportedExtensions : 1; + /// Enable Provenance to character-stream mapping. Allows e.g. IDEs to find /// symbols based on source-code location. This is not needed in regular /// compilation. diff --git a/flang/lib/Frontend/CompilerInvocation.cpp b/flang/lib/Frontend/CompilerInvocation.cpp index 0b79c95eade0d3..32a79e55989509 100644 --- a/flang/lib/Frontend/CompilerInvocation.cpp +++ b/flang/lib/Frontend/CompilerInvocation.cpp @@ -636,6 +636,8 @@ static bool parseFrontendArgs(FrontendOptions &opts, llvm::opt::ArgList &args, opts.showVersion = args.hasArg(clang::driver::options::OPT_version); opts.printSupportedCPUs = args.hasArg(clang::driver::options::OPT_print_supported_cpus); + opts.printSupportedExtensions = + args.hasArg(clang::driver::options::OPT_print_supported_extensions); // Get the input kind (from the value passed via `-x`) InputKind dashX(Language::Unknown); diff --git a/flang/test/Driver/print-supported-extensions-aarch64.f90 b/flang/test/Driver/print-supported-extensions-aarch64.f90 new file mode 100644 index 00000000000000..5e5ed0dc0625df --- /dev/null +++ b/flang/test/Driver/print-supported-extensions-aarch64.f90 @@ -0,0 +1,104 @@ +! REQUIRES: aarch64-registered-target + +! RUN: %flang --target=aarch64-linux-gnu --print-supported-extensions 2>&1 \ +! RUN: | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s + +! CHECK: All available -march extensions for AArch64 +! CHECK-EMPTY: +! CHECK-NEXT: Name Architecture Feature(s) Description +! CHECK-NEXT: aes FEAT_AES, FEAT_PMULL Enable AES support +! CHECK-NEXT: bf16 FEAT_BF16 Enable BFloat16 Extension +! CHECK-NEXT: brbe FEAT_BRBE Enable Branch Record Buffer Extension +! CHECK-NEXT: bti FEAT_BTI Enable Branch Target Identification +! CHECK-NEXT: cmpbr FEAT_CMPBR Enable Armv9.6-A base compare and branch instructions +! CHECK-NEXT: fcma FEAT_FCMA Enable Armv8.3-A Floating-point complex number support +! CHECK-NEXT: cpa FEAT_CPA Enable Armv9.5-A Checked Pointer Arithmetic +! CHECK-NEXT: crc FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions +! CHECK-NEXT: crypto FEAT_Crypto Enable cryptographic instructions +! CHECK-NEXT: cssc FEAT_CSSC Enable Common Short Sequence Compression (CSSC) instructions +! CHECK-NEXT: d128 FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, FEAT_SYSINSTR128 Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers and instructions +! CHECK-NEXT: dit FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions +! CHECK-NEXT: dotprod FEAT_DotProd Enable dot product support +! CHECK-NEXT: f32mm FEAT_F32MM Enable Matrix Multiply FP32 Extension +! CHECK-NEXT: f64mm FEAT_F64MM Enable Matrix Multiply FP64 Extension +! CHECK-NEXT: f8f16mm FEAT_F8F16MM Enable Armv9.6-A FP8 to Half-Precision Matrix Multiplication +! CHECK-NEXT: f8f32mm FEAT_F8F32MM Enable Armv9.6-A FP8 to Single-Precision Matrix Multiplication +! CHECK-NEXT: faminmax FEAT_FAMINMAX Enable FAMIN and FAMAX instructions +! CHECK-NEXT: flagm FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions +! CHECK-NEXT: fp FEAT_FP Enable Armv8.0-A Floating Point Extensions +! CHECK-NEXT: fp16fml FEAT_FHM Enable FP16 FML instructions +! CHECK-NEXT: fp8 FEAT_FP8 Enable FP8 instructions +! CHECK-NEXT: fp8dot2 FEAT_FP8DOT2 Enable FP8 2-way dot instructions +! CHECK-NEXT: fp8dot4 FEAT_FP8DOT4 Enable FP8 4-way dot instructions +! CHECK-NEXT: fp8fma FEAT_FP8FMA Enable Armv9.5-A FP8 multiply-add instructions +! CHECK-NEXT: fprcvt FEAT_FPRCVT Enable Armv9.6-A base convert instructions for SIMD&FP scalar register operands of different input and output sizes +! CHECK-NEXT: fp16 FEAT_FP16 Enable half-precision floating-point data processing +! CHECK-NEXT: gcs FEAT_GCS Enable Armv9.4-A Guarded Call Stack Extension +! CHECK-NEXT: hbc FEAT_HBC Enable Armv8.8-A Hinted Conditional Branches Extension +! CHECK-NEXT: i8mm FEAT_I8MM Enable Matrix Multiply Int8 Extension +! CHECK-NEXT: ite FEAT_ITE Enable Armv9.4-A Instrumentation Extension +! CHECK-NEXT: jscvt FEAT_JSCVT Enable Armv8.3-A JavaScript FP conversion instructions +! CHECK-NEXT: ls64 FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA Enable Armv8.7-A LD64B/ST64B Accelerator Extension +! CHECK-NEXT: lse FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions +! CHECK-NEXT: lse128 FEAT_LSE128 Enable Armv9.4-A 128-bit Atomic instructions +! CHECK-NEXT: lsfe FEAT_LSFE Enable Armv9.6-A base Atomic floating-point in-memory instructions +! CHECK-NEXT: lsui FEAT_LSUI Enable Armv9.6-A unprivileged load/store instructions +! CHECK-NEXT: lut FEAT_LUT Enable Lookup Table instructions +! CHECK-NEXT: mops FEAT_MOPS Enable Armv8.8-A memcpy and memset acceleration instructions +! CHECK-NEXT: memtag FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension +! CHECK-NEXT: simd FEAT_AdvSIMD Enable Advanced SIMD instructions +! CHECK-NEXT: occmo FEAT_OCCMO Enable Armv9.6-A Outer cacheable cache maintenance operations +! CHECK-NEXT: pauth FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension +! CHECK-NEXT: pauth-lr FEAT_PAuth_LR Enable Armv9.5-A PAC enhancements +! CHECK-NEXT: pcdphint FEAT_PCDPHINT Enable Armv9.6-A Producer Consumer Data Placement hints +! CHECK-NEXT: pmuv3 FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension +! CHECK-NEXT: pops FEAT_PoPS Enable Armv9.6-A Point Of Physical Storage (PoPS) DC instructions +! CHECK-NEXT: predres FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions +! CHECK-NEXT: rng FEAT_RNG Enable Random Number generation instructions +! CHECK-NEXT: ras FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions +! CHECK-NEXT: rasv2 FEAT_RASv2 Enable Armv8.9-A Reliability, Availability and Serviceability Extensions +! CHECK-NEXT: rcpc FEAT_LRCPC Enable support for RCPC extension +! CHECK-NEXT: rcpc3 FEAT_LRCPC3 Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set +! CHECK-NEXT: rdm FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions +! CHECK-NEXT: sb FEAT_SB Enable Armv8.5-A Speculation Barrier +! CHECK-NEXT: sha2 FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support +! CHECK-NEXT: sha3 FEAT_SHA3, FEAT_SHA512 Enable SHA512 and SHA3 support +! CHECK-NEXT: sm4 FEAT_SM4, FEAT_SM3 Enable SM3 and SM4 support +! CHECK-NEXT: sme FEAT_SME Enable Scalable Matrix Extension (SME) +! CHECK-NEXT: sme-b16b16 FEAT_SME_B16B16 Enable SME2.1 ZA-targeting non-widening BFloat16 instructions +! CHECK-NEXT: sme-f16f16 FEAT_SME_F16F16 Enable SME non-widening Float16 instructions +! CHECK-NEXT: sme-f64f64 FEAT_SME_F64F64 Enable Scalable Matrix Extension (SME) F64F64 instructions +! CHECK-NEXT: sme-f8f16 FEAT_SME_F8F16 Enable Scalable Matrix Extension (SME) F8F16 instructions +! CHECK-NEXT: sme-f8f32 FEAT_SME_F8F32 Enable Scalable Matrix Extension (SME) F8F32 instructions +! CHECK-NEXT: sme-fa64 FEAT_SME_FA64 Enable the full A64 instruction set in streaming SVE mode +! CHECK-NEXT: sme-i16i64 FEAT_SME_I16I64 Enable Scalable Matrix Extension (SME) I16I64 instructions +! CHECK-NEXT: sme-lutv2 FEAT_SME_LUTv2 Enable Scalable Matrix Extension (SME) LUTv2 instructions +! CHECK-NEXT: sme2 FEAT_SME2 Enable Scalable Matrix Extension 2 (SME2) instructions +! CHECK-NEXT: sme2p1 FEAT_SME2p1 Enable Scalable Matrix Extension 2.1 instructions +! CHECK-NEXT: sme2p2 FEAT_SME2p2 Enable Armv9.6-A Scalable Matrix Extension 2.2 instructions +! CHECK-NEXT: profile FEAT_SPE Enable Statistical Profiling extension +! CHECK-NEXT: predres2 FEAT_SPECRES2 Enable Speculation Restriction Instruction +! CHECK-NEXT: ssbs FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit +! CHECK-NEXT: ssve-aes FEAT_SSVE_AES Enable Armv9.6-A SVE AES support in streaming SVE mode +! CHECK-NEXT: ssve-fp8dot2 FEAT_SSVE_FP8DOT2 Enable SVE2 FP8 2-way dot product instructions +! CHECK-NEXT: ssve-fp8dot4 FEAT_SSVE_FP8DOT4 Enable SVE2 FP8 4-way dot product instructions +! CHECK-NEXT: ssve-fp8fma FEAT_SSVE_FP8FMA Enable SVE2 FP8 multiply-add instructions +! CHECK-NEXT: sve FEAT_SVE Enable Scalable Vector Extension (SVE) instructions +! CHECK-NEXT: sve-aes FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable SVE AES and quadword SVE polynomial multiply instructions +! CHECK-NEXT: sve-aes2 FEAT_SVE_AES2 Enable Armv9.6-A SVE multi-vector AES and multi-vector quadword polynomial multiply instructions +! CHECK-NEXT: sve-b16b16 FEAT_SVE_B16B16 Enable SVE2 non-widening and SME2 Z-targeting non-widening BFloat16 instructions +! CHECK-NEXT: sve-bfscale FEAT_SVE_BFSCALE Enable Armv9.6-A SVE BFloat16 scaling instructions +! CHECK-NEXT: sve-f16f32mm FEAT_SVE_F16F32MM Enable Armv9.6-A FP16 to FP32 Matrix Multiply +! CHECK-NEXT: sve2 FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions +! CHECK-NEXT: sve2-aes Shorthand for +sve2+sve-aes +! CHECK-NEXT: sve2-bitperm FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions +! CHECK-NEXT: sve2-sha3 FEAT_SVE_SHA3 Enable SHA3 SVE2 instructions +! CHECK-NEXT: sve2-sm4 FEAT_SVE_SM4 Enable SM4 SVE2 instructions +! CHECK-NEXT: sve2p1 FEAT_SVE2p1 Enable Scalable Vector Extension 2.1 instructions +! CHECK-NEXT: sve2p2 FEAT_SVE2p2 Enable Armv9.6-A Scalable Vector Extension 2.2 instructions +! CHECK-NEXT: the FEAT_THE Enable Armv8.9-A Translation Hardening Extension +! CHECK-NEXT: tlbiw FEAT_TLBIW Enable Armv9.5-A TLBI VMALL for Dirty State +! CHECK-NEXT: tme FEAT_TME Enable Transactional Memory Extension +! CHECK-NEXT: wfxt FEAT_WFxT Enable Armv8.7-A WFET and WFIT instruction + +end program diff --git a/flang/test/Driver/print-supported-extensions-arm.f90 b/flang/test/Driver/print-supported-extensions-arm.f90 new file mode 100644 index 00000000000000..3e5de541f9a119 --- /dev/null +++ b/flang/test/Driver/print-supported-extensions-arm.f90 @@ -0,0 +1,34 @@ +! REQUIRES: arm-registered-target + +! RUN: %flang --target=arm-linux-gnu --print-supported-extensions 2>&1 \ +! RUN: | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s + +! CHECK: All available -march extensions for ARM +! CHECK-EMPTY: +! CHECK-NEXT: Name Description +! CHECK-NEXT: crc Enable support for CRC instructions +! CHECK-NEXT: crypto Enable support for Cryptography extensions +! CHECK-NEXT: sha2 Enable SHA1 and SHA256 support +! CHECK-NEXT: aes Enable AES support +! CHECK-NEXT: dotprod Enable support for dot product instructions +! CHECK-NEXT: dsp Supports DSP instructions in ARM and/or Thumb2 +! CHECK-NEXT: mve Support M-Class Vector Extension with integer ops +! CHECK-NEXT: mve.fp Support M-Class Vector Extension with integer and floating ops +! CHECK-NEXT: fp16 Enable half-precision floating point +! CHECK-NEXT: ras Enable Reliability, Availability and Serviceability extensions +! CHECK-NEXT: fp16fml Enable full half-precision floating point fml instructions +! CHECK-NEXT: bf16 Enable support for BFloat16 instructions +! CHECK-NEXT: sb Enable v8.5a Speculation Barrier +! CHECK-NEXT: i8mm Enable Matrix Multiply Int8 Extension +! CHECK-NEXT: lob Enable Low Overhead Branch extensions +! CHECK-NEXT: cdecp0 Coprocessor 0 ISA is CDEv1 +! CHECK-NEXT: cdecp1 Coprocessor 1 ISA is CDEv1 +! CHECK-NEXT: cdecp2 Coprocessor 2 ISA is CDEv1 +! CHECK-NEXT: cdecp3 Coprocessor 3 ISA is CDEv1 +! CHECK-NEXT: cdecp4 Coprocessor 4 ISA is CDEv1 +! CHECK-NEXT: cdecp5 Coprocessor 5 ISA is CDEv1 +! CHECK-NEXT: cdecp6 Coprocessor 6 ISA is CDEv1 +! CHECK-NEXT: cdecp7 Coprocessor 7 ISA is CDEv1 +! CHECK-NEXT: pacbti Enable Pointer Authentication and Branch Target Identification + +end program diff --git a/flang/test/Driver/print-supported-extensions-riscv.f90 b/flang/test/Driver/print-supported-extensions-riscv.f90 new file mode 100644 index 00000000000000..4bb24e64926ebb --- /dev/null +++ b/flang/test/Driver/print-supported-extensions-riscv.f90 @@ -0,0 +1,211 @@ +! REQUIRES: riscv-registered-target + +! RUN: %flang --target=riscv64-linux-gnu --print-supported-extensions 2>&1 \ +! RUN: | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s + +! CHECK: All available -march extensions for RISC-V +! CHECK-EMPTY: +! CHECK-NEXT: Name Version Description +! CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set) +! CHECK-NEXT: e 2.0 Implements RV{32,64}E (provides 16 rather than 32 GPRs) +! CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division) +! CHECK-NEXT: a 2.1 'A' (Atomic Instructions) +! CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point) +! CHECK-NEXT: d ... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/117402 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
