Author: Brandon Wu Date: 2024-11-23T01:41:12+08:00 New Revision: 05b3d26181ade32f5988d2be4939f605a5225782
URL: https://github.com/llvm/llvm-project/commit/05b3d26181ade32f5988d2be4939f605a5225782 DIFF: https://github.com/llvm/llvm-project/commit/05b3d26181ade32f5988d2be4939f605a5225782.diff LOG: [clang][RISCV] Bump RVV intrinsic to version 1.0 (#116597) The spec: https://github.com/riscv-non-isa/rvv-intrinsic-doc/releases/tag/v1.0.0-rc4 Also remove __riscv_v_intrinsic_overloading since it's no longer in spec, the overloading intrinsics should be also enabled when RVV intrinsics are defined. Added: Modified: clang/docs/ReleaseNotes.rst clang/lib/Basic/Targets/RISCV.cpp clang/test/Preprocessor/riscv-target-features.c clang/utils/TableGen/RISCVVEmitter.cpp Removed: ################################################################################ diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 54145b28154eb4..8bd06fadfdc984 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -852,6 +852,7 @@ RISC-V Support ^^^^^^^^^^^^^^ - The option ``-mcmodel=large`` for the large code model is supported. +- Bump RVV intrinsic to version 1.0, the spec: https://github.com/riscv-non-isa/rvv-intrinsic-doc/releases/tag/v1.0.0-rc4 CUDA/HIP Language Changes ^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index 2384b322c50f92..f0623070319e1f 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -218,8 +218,8 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts, if (ISAInfo->hasExtension("zve32x")) { Builder.defineMacro("__riscv_vector"); - // Currently we support the v0.12 RISC-V V intrinsics. - Builder.defineMacro("__riscv_v_intrinsic", Twine(getVersionValue(0, 12))); + // Currently we support the v1.0 RISC-V V intrinsics. + Builder.defineMacro("__riscv_v_intrinsic", Twine(getVersionValue(1, 0))); } auto VScale = getVScaleRange(Opts); diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 7e8d1fa2448b80..13125d749c5fab 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -536,7 +536,7 @@ // CHECK-V-EXT: __riscv_v 1000000{{$}} // CHECK-V-EXT: __riscv_v_elen 64 // CHECK-V-EXT: __riscv_v_elen_fp 64 -// CHECK-V-EXT: __riscv_v_intrinsic 12000{{$}} +// CHECK-V-EXT: __riscv_v_intrinsic 1000000{{$}} // CHECK-V-EXT: __riscv_v_min_vlen 128 // CHECK-V-EXT: __riscv_vector 1 @@ -1244,7 +1244,7 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVE32F-EXT %s // CHECK-ZVE32F-EXT: __riscv_v_elen 32 // CHECK-ZVE32F-EXT: __riscv_v_elen_fp 32 -// CHECK-ZVE32F-EXT: __riscv_v_intrinsic 12000{{$}} +// CHECK-ZVE32F-EXT: __riscv_v_intrinsic 1000000{{$}} // CHECK-ZVE32F-EXT: __riscv_v_min_vlen 32 // CHECK-ZVE32F-EXT: __riscv_vector 1 // CHECK-ZVE32F-EXT: __riscv_zve32f 1000000{{$}} @@ -1258,7 +1258,7 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVE32X-EXT %s // CHECK-ZVE32X-EXT: __riscv_v_elen 32 // CHECK-ZVE32X-EXT: __riscv_v_elen_fp 0 -// CHECK-ZVE32X-EXT: __riscv_v_intrinsic 12000{{$}} +// CHECK-ZVE32X-EXT: __riscv_v_intrinsic 1000000{{$}} // CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32 // CHECK-ZVE32X-EXT: __riscv_vector 1 // CHECK-ZVE32X-EXT: __riscv_zve32x 1000000{{$}} @@ -1271,7 +1271,7 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVE64D-EXT %s // CHECK-ZVE64D-EXT: __riscv_v_elen 64 // CHECK-ZVE64D-EXT: __riscv_v_elen_fp 64 -// CHECK-ZVE64D-EXT: __riscv_v_intrinsic 12000{{$}} +// CHECK-ZVE64D-EXT: __riscv_v_intrinsic 1000000{{$}} // CHECK-ZVE64D-EXT: __riscv_v_min_vlen 64 // CHECK-ZVE64D-EXT: __riscv_vector 1 // CHECK-ZVE64D-EXT: __riscv_zve32f 1000000{{$}} @@ -1288,7 +1288,7 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVE64F-EXT %s // CHECK-ZVE64F-EXT: __riscv_v_elen 64 // CHECK-ZVE64F-EXT: __riscv_v_elen_fp 32 -// CHECK-ZVE64F-EXT: __riscv_v_intrinsic 12000{{$}} +// CHECK-ZVE64F-EXT: __riscv_v_intrinsic 1000000{{$}} // CHECK-ZVE64F-EXT: __riscv_v_min_vlen 64 // CHECK-ZVE64F-EXT: __riscv_vector 1 // CHECK-ZVE64F-EXT: __riscv_zve32f 1000000{{$}} @@ -1304,7 +1304,7 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVE64X-EXT %s // CHECK-ZVE64X-EXT: __riscv_v_elen 64 // CHECK-ZVE64X-EXT: __riscv_v_elen_fp 0 -// CHECK-ZVE64X-EXT: __riscv_v_intrinsic 12000{{$}} +// CHECK-ZVE64X-EXT: __riscv_v_intrinsic 1000000{{$}} // CHECK-ZVE64X-EXT: __riscv_v_min_vlen 64 // CHECK-ZVE64X-EXT: __riscv_vector 1 // CHECK-ZVE64X-EXT: __riscv_zve32x 1000000{{$}} diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp index 68d7831c117458..acba1a31912816 100644 --- a/clang/utils/TableGen/RISCVVEmitter.cpp +++ b/clang/utils/TableGen/RISCVVEmitter.cpp @@ -488,8 +488,6 @@ void RVVEmitter::createHeader(raw_ostream &OS) { } } - OS << "#define __riscv_v_intrinsic_overloading 1\n"; - OS << "\n#ifdef __cplusplus\n"; OS << "}\n"; OS << "#endif // __cplusplus\n"; _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
