Author: Matt Arsenault Date: 2024-11-21T09:08:15-08:00 New Revision: f4ed79b160cbd2ec537304f095a62750078a0254
URL: https://github.com/llvm/llvm-project/commit/f4ed79b160cbd2ec537304f095a62750078a0254 DIFF: https://github.com/llvm/llvm-project/commit/f4ed79b160cbd2ec537304f095a62750078a0254.diff LOG: AMDGPU: Add v_mfma_i32_32x32x32_i8 for gfx950 (#117052) Added: Modified: clang/include/clang/Basic/BuiltinsAMDGPU.def clang/test/CodeGenOpenCL/builtins-amdgcn-mfma.cl clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950.cl llvm/include/llvm/IR/IntrinsicsAMDGPU.td llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp llvm/lib/Target/AMDGPU/VOP3PInstructions.td llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll llvm/test/MC/AMDGPU/mai-gfx950.s llvm/test/MC/Disassembler/AMDGPU/gfx950_mai.txt llvm/test/tools/llvm-mca/AMDGPU/gfx950.s Removed: ################################################################################ diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.def b/clang/include/clang/Basic/BuiltinsAMDGPU.def index b4c7c12fec6475..6c51e52a2ef665 100644 --- a/clang/include/clang/Basic/BuiltinsAMDGPU.def +++ b/clang/include/clang/Basic/BuiltinsAMDGPU.def @@ -441,6 +441,7 @@ TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_16x16x32_f16, "V4fV8hV8hV4fIiIiIi", "nc TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_32x32x16_f16, "V16fV8hV8hV16fIiIiIi", "nc", "gfx950-insts") TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_32x32x16_bf16, "V16fV8yV8yV16fIiIiIi", "nc", "gfx950-insts") TARGET_BUILTIN(__builtin_amdgcn_mfma_i32_16x16x64_i8, "V4iV4iV4iV4iIiIiIi", "nc", "gfx950-insts") +TARGET_BUILTIN(__builtin_amdgcn_mfma_i32_32x32x32_i8, "V16iV4iV4iV16iIiIiIi", "nc", "gfx950-insts") //===----------------------------------------------------------------------===// // GFX12+ only builtins. diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-mfma.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-mfma.cl index 6ab7ca12368103..1fcd6597e2da2f 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn-mfma.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-mfma.cl @@ -454,4 +454,10 @@ v4i test_mfma_i32_16x16x64_i8(v4i a, v4i b, v4i c) { return __builtin_amdgcn_mfma_i32_16x16x64_i8(a, b, c, 1, 2, 3); } +// CHECK-GFX950-LABEL: @test_mfma_i32_32x32x32_i8( +// CHECK-GFX950: tail call <16 x i32> @llvm.amdgcn.mfma.i32.32x32x32.i8(<4 x i32> %a, <4 x i32> %b, <16 x i32> %c, i32 1, i32 2, i32 3) +v16i test_mfma_i32_32x32x32_i8(v4i a, v4i b, v16i c) { + return __builtin_amdgcn_mfma_i32_32x32x32_i8(a, b, c, 1, 2, 3); +} + #endif diff --git a/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl b/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl index 3597042fadcf88..9c14c0541ff3b8 100644 --- a/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl +++ b/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl @@ -7,6 +7,7 @@ typedef half half8 __attribute__((ext_vector_type(8))); typedef __bf16 bfloat8 __attribute__((ext_vector_type(8))); typedef int int4 __attribute__((ext_vector_type(4))); typedef int int8 __attribute__((ext_vector_type(8))); +typedef int int16 __attribute__((ext_vector_type(16))); void test_mfma_f32_16x16x32_f16(__global float4* out, half8 a, half8 b, float4 c, int X) { @@ -48,3 +49,9 @@ void test_mfma_i32_16x16x64_i8(__global int4* out, int4 a, int4 b, int4 c, int X *out = __builtin_amdgcn_mfma_i32_16x16x64_i8(a, b, c, 0, X, 0); // expected-error{{argument to '__builtin_amdgcn_mfma_i32_16x16x64_i8' must be a constant integer}} *out = __builtin_amdgcn_mfma_i32_16x16x64_i8(a, b, c, 0, 0, X); // expected-error{{argument to '__builtin_amdgcn_mfma_i32_16x16x64_i8' must be a constant integer}} } + +void test_mfma_i32_32x32x32_i8(__global int16* out, int4 a, int4 b, int16 c, int X) { + *out = __builtin_amdgcn_mfma_i32_32x32x32_i8(a, b, c, X, 0, 0); // expected-error{{argument to '__builtin_amdgcn_mfma_i32_32x32x32_i8' must be a constant integer}} + *out = __builtin_amdgcn_mfma_i32_32x32x32_i8(a, b, c, 0, X, 0); // expected-error{{argument to '__builtin_amdgcn_mfma_i32_32x32x32_i8' must be a constant integer}} + *out = __builtin_amdgcn_mfma_i32_32x32x32_i8(a, b, c, 0, 0, X); // expected-error{{argument to '__builtin_amdgcn_mfma_i32_32x32x32_i8' must be a constant integer}} +} diff --git a/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950.cl b/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950.cl index 3a27fbf2439353..71a110066342cb 100644 --- a/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950.cl +++ b/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950.cl @@ -32,6 +32,7 @@ void test(__global float4* out0, half8 a0, half8 b0, float4 c0, *out1 = __builtin_amdgcn_mfma_f32_32x32x16_f16(a1, b1, c1, 0, 0, 0); // expected-error{{'__builtin_amdgcn_mfma_f32_32x32x16_f16' needs target feature gfx950-insts}} *out2 = __builtin_amdgcn_mfma_f32_32x32x16_bf16(a2, b2, c2, 0, 0, 0); // expected-error{{'__builtin_amdgcn_mfma_f32_32x32x16_bf16' needs target feature gfx950-insts}} *out3 = __builtin_amdgcn_mfma_i32_16x16x64_i8(a3, b3, c3, 0, 0, 0); // expected-error{{'__builtin_amdgcn_mfma_i32_16x16x64_i8' needs target feature gfx950-insts}} + *out4 = __builtin_amdgcn_mfma_i32_32x32x32_i8(a4, b4, c4, 0, 0, 0); // expected-error{{'__builtin_amdgcn_mfma_i32_32x32x32_i8' needs target feature gfx950-insts}} *out14 = __builtin_amdgcn_mfma_scale_f32_16x16x128_f8f6f4(a14, b14, c14, 0, 0, 0, d14, 0, e14); // expected-error{{'__builtin_amdgcn_mfma_scale_f32_16x16x128_f8f6f4' needs target feature gfx950-insts}} *out15 = __builtin_amdgcn_mfma_scale_f32_32x32x64_f8f6f4(a15, b15, c15, 0, 0, 0, d15, 0, e15); // expected-error{{'__builtin_amdgcn_mfma_scale_f32_32x32x64_f8f6f4' needs target feature gfx950-insts}} } diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td index 35f45095b1ad04..b5d5eae0c7cd7e 100644 --- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td +++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td @@ -3147,6 +3147,7 @@ defset list<Intrinsic> AMDGPUMFMAIntrinsics950 = { def int_amdgcn_mfma_f32_16x16x32_f16 : AMDGPUMfmaIntrinsic<llvm_v4f32_ty, llvm_v8f16_ty>; def int_amdgcn_mfma_f32_32x32x16_f16 : AMDGPUMfmaIntrinsic<llvm_v16f32_ty, llvm_v8f16_ty>; def int_amdgcn_mfma_i32_16x16x64_i8 : AMDGPUMfmaIntrinsic<llvm_v4i32_ty, llvm_v4i32_ty>; +def int_amdgcn_mfma_i32_32x32x32_i8 : AMDGPUMfmaIntrinsic<llvm_v16i32_ty, llvm_v4i32_ty>; def int_amdgcn_mfma_f32_32x32x16_bf16 : AMDGPUMfmaIntrinsic<llvm_v16f32_ty, llvm_v8bf16_ty>; def int_amdgcn_mfma_scale_f32_16x16x128_f8f6f4 : AMDGPUMfmaScaleIntrinsic<llvm_v4f32_ty>; diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index f8ef1879496bb2..ea9c688c710418 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -4750,7 +4750,8 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_fp8: case Intrinsic::amdgcn_mfma_f32_16x16x32_f16: case Intrinsic::amdgcn_mfma_f32_32x32x16_f16: - case Intrinsic::amdgcn_mfma_i32_16x16x64_i8: { + case Intrinsic::amdgcn_mfma_i32_16x16x64_i8: + case Intrinsic::amdgcn_mfma_i32_32x32x32_i8: { // Default for MAI intrinsics. // srcC can also be an immediate which can be folded later. // FIXME: Should we eventually add an alternative mapping with AGPR src diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td index 7a83e76ba4c919..98d5e3f199cddd 100644 --- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td @@ -725,6 +725,10 @@ def VOPProfileMAI_F32_V4I32_V4I32_X512_VCD : VOPProfileMAI<VOP_V16F32_V4I32_V4I3 def VOPProfileMAI_I32_V4I32_X128 : VOPProfileMAI<VOP_V4I32_V4I32_V4I32_V4I32, AISrc_128_f32, ADst_128, AVSrc_128>; def VOPProfileMAI_I32_V4I32_X128_VCD : VOPProfileMAI<VOP_V4I32_V4I32_V4I32_V4I32, VISrc_128_f32, VDst_128, AVSrc_128>; +// For i32_32x32x32_i8 +def VOPProfileMAI_I32_V4I32_X16 : VOPProfileMAI<VOP_V16I32_V4I32_V4I32_V16I32, AISrc_512_b32, ADst_512, AVSrc_128>; +def VOPProfileMAI_I32_V4I32_X16_VCD : VOPProfileMAI<VOP_V16I32_V4I32_V4I32_V16I32, VISrc_512_b32, VDst_512, AVSrc_128>; + class MFMATable <bit is_mac, string Name> { bit IsMac = is_mac; @@ -950,6 +954,7 @@ defm V_MFMA_F32_16X16X32_F16 : MAIInst<"v_mfma_f32_16x16x32f16", "F32_V8F16 defm V_MFMA_F32_32X32X16_F16 : MAIInst<"v_mfma_f32_32x32x16f16", "F32_V8F16_X16", int_amdgcn_mfma_f32_32x32x16_f16>; defm V_MFMA_I32_16X16X64_I8 : MAIInst<"v_mfma_i32_16x16x64i8", "I32_V4I32_X128", int_amdgcn_mfma_i32_16x16x64_i8>; defm V_MFMA_F32_32X32X16_BF16 : MAIInst<"v_mfma_f32_32x32x16bf16", "F32_V8BF16_X16", int_amdgcn_mfma_f32_32x32x16_bf16>; +defm V_MFMA_I32_32X32X32_I8 : MAIInst<"v_mfma_i32_32x32x32i8", "I32_V4I32_X16", int_amdgcn_mfma_i32_32x32x32_i8>; defm V_MFMA_F32_16X16X128_F8F6F4 : MAIInst_SrcFormats_mc<"v_mfma_f32_16x16x128f8f6f4", "_X128", mfma_f32_16x16x128_f8f6f4>; @@ -2075,6 +2080,7 @@ defm V_MFMA_F32_16X16X32_F16 : VOP3P_Real_MFMA_gfx950 <0x54, "v_mfma_f32_16x defm V_MFMA_F32_32X32X16_F16 : VOP3P_Real_MFMA_gfx950 <0x55, "v_mfma_f32_32x32x16_f16">; defm V_MFMA_I32_16X16X64_I8 : VOP3P_Real_MFMA_gfx950 <0x36, "v_mfma_i32_16x16x64_i8">; defm V_MFMA_F32_32X32X16_BF16 : VOP3P_Real_MFMA_gfx950 <0x37, "v_mfma_f32_32x32x16_bf16">; +defm V_MFMA_I32_32X32X32_I8 : VOP3P_Real_MFMA_gfx950 <0x38, "v_mfma_i32_32x32x32_i8">; defm V_MFMA_LD_SCALE_B32 : VOP3P_Real_vi <0x2c>; defm V_MFMA_F32_16X16X128_F8F6F4 : VOP3P_Real_MFMA_F8F6F4_gfx950_mc <0x2d, "v_mfma_f32_16x16x128_f8f6f4">; diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll index 48c6c42b66b9a5..26021a56790aae 100644 --- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll +++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll @@ -314,6 +314,15 @@ define amdgpu_kernel void @mfma_i32_16x16x64_i8(<4 x i32> %arg0, <4 x i32> %arg1 ret void } +declare <16 x i32> @llvm.amdgcn.mfma.i32.32x32x32.i8(<4 x i32>, <4 x i32>, <16 x i32>, i32 immarg, i32 immarg, i32 immarg) + +; CHECK: DIVERGENT: %result = call <16 x i32> @llvm.amdgcn.mfma.i32.32x32x32.i8(<4 x i32> %arg0, <4 x i32> %arg1, <16 x i32> %arg2, i32 immarg 0, i32 immarg 0, i32 immarg 0) +define amdgpu_kernel void @mfma_i32_32x32x32_i8(<4 x i32> %arg0, <4 x i32> %arg1, <16 x i32> %arg2, ptr addrspace(1) %out) { + %result = call <16 x i32> @llvm.amdgcn.mfma.i32.32x32x32.i8(<4 x i32> %arg0, <4 x i32> %arg1, <16 x i32> %arg2, i32 immarg 0, i32 immarg 0, i32 immarg 0) + store <16 x i32> %result, ptr addrspace(1) %out + ret void +} + declare i32 @llvm.amdgcn.ds.swizzle(i32, i32) #1 declare i32 @llvm.amdgcn.permlane16.i32(i32, i32, i32, i32, i1, i1) #1 declare i32 @llvm.amdgcn.permlanex16.i32(i32, i32, i32, i32, i1, i1) #1 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll index 555756d3fdf3f8..29668b2c5bfdbf 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll @@ -555,5 +555,765 @@ define amdgpu_kernel void @test_mfma_i32_16x16x64_i8_no_agpr__vgprcd__flags(ptr ret void } +; -------------------------------------------------------------------- +; llvm.amdgcn.mfma.i32.32x32x32.i8 +; -------------------------------------------------------------------- + +declare <16 x i32> @llvm.amdgcn.mfma.i32.32x32x32.i8(<4 x i32>, <4 x i32>, <16 x i32>, i32 immarg, i32 immarg, i32 immarg) + +define amdgpu_kernel void @test_mfma_i32_32x32x32_i8(<4 x i32> %arg0, <4 x i32> %arg1, <16 x i32> %arg2) #1 { +; SDAG-LABEL: test_mfma_i32_32x32x32_i8: +; SDAG: ; %bb.0: +; SDAG-NEXT: s_load_dwordx8 s[20:27], s[0:1], 0x24 +; SDAG-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x64 +; SDAG-NEXT: v_mov_b64_e32 v[8:9], 16 +; SDAG-NEXT: v_mov_b64_e32 v[10:11], 0 +; SDAG-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-NEXT: v_mov_b32_e32 v0, s20 +; SDAG-NEXT: v_accvgpr_write_b32 a31, s19 +; SDAG-NEXT: v_mov_b32_e32 v1, s21 +; SDAG-NEXT: v_mov_b32_e32 v2, s22 +; SDAG-NEXT: v_mov_b32_e32 v3, s23 +; SDAG-NEXT: v_mov_b32_e32 v4, s24 +; SDAG-NEXT: v_mov_b32_e32 v5, s25 +; SDAG-NEXT: v_mov_b32_e32 v6, s26 +; SDAG-NEXT: v_mov_b32_e32 v7, s27 +; SDAG-NEXT: v_accvgpr_write_b32 a30, s18 +; SDAG-NEXT: v_accvgpr_write_b32 a29, s17 +; SDAG-NEXT: v_accvgpr_write_b32 a28, s16 +; SDAG-NEXT: v_accvgpr_write_b32 a27, s15 +; SDAG-NEXT: v_accvgpr_write_b32 a26, s14 +; SDAG-NEXT: v_accvgpr_write_b32 a25, s13 +; SDAG-NEXT: v_accvgpr_write_b32 a24, s12 +; SDAG-NEXT: v_accvgpr_write_b32 a23, s11 +; SDAG-NEXT: v_accvgpr_write_b32 a22, s10 +; SDAG-NEXT: v_accvgpr_write_b32 a21, s9 +; SDAG-NEXT: v_accvgpr_write_b32 a20, s8 +; SDAG-NEXT: v_accvgpr_write_b32 a19, s7 +; SDAG-NEXT: v_accvgpr_write_b32 a18, s6 +; SDAG-NEXT: v_accvgpr_write_b32 a17, s5 +; SDAG-NEXT: v_accvgpr_write_b32 a16, s4 +; SDAG-NEXT: s_nop 1 +; SDAG-NEXT: v_mfma_i32_32x32x32_i8 a[0:15], v[0:3], v[4:7], a[16:31] +; SDAG-NEXT: v_mov_b64_e32 v[4:5], 48 +; SDAG-NEXT: v_mov_b64_e32 v[6:7], 32 +; SDAG-NEXT: v_mov_b32_e32 v0, s12 +; SDAG-NEXT: v_mov_b32_e32 v1, s13 +; SDAG-NEXT: v_mov_b32_e32 v2, s14 +; SDAG-NEXT: v_mov_b32_e32 v3, s15 +; SDAG-NEXT: s_nop 7 +; SDAG-NEXT: s_nop 4 +; SDAG-NEXT: global_store_dwordx4 v[4:5], a[12:15], off sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: global_store_dwordx4 v[6:7], a[8:11], off sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: global_store_dwordx4 v[8:9], a[4:7], off sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: global_store_dwordx4 v[10:11], a[0:3], off sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: global_store_dwordx4 v[6:7], v[0:3], off sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: s_nop 0 +; SDAG-NEXT: v_mov_b32_e32 v0, s16 +; SDAG-NEXT: v_mov_b32_e32 v1, s17 +; SDAG-NEXT: v_mov_b32_e32 v2, s18 +; SDAG-NEXT: v_mov_b32_e32 v3, s19 +; SDAG-NEXT: global_store_dwordx4 v[4:5], v[0:3], off sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: s_nop 0 +; SDAG-NEXT: v_mov_b32_e32 v0, s4 +; SDAG-NEXT: v_mov_b32_e32 v1, s5 +; SDAG-NEXT: v_mov_b32_e32 v2, s6 +; SDAG-NEXT: v_mov_b32_e32 v3, s7 +; SDAG-NEXT: global_store_dwordx4 v[10:11], v[0:3], off sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: s_nop 0 +; SDAG-NEXT: v_mov_b32_e32 v0, s8 +; SDAG-NEXT: v_mov_b32_e32 v1, s9 +; SDAG-NEXT: v_mov_b32_e32 v2, s10 +; SDAG-NEXT: v_mov_b32_e32 v3, s11 +; SDAG-NEXT: global_store_dwordx4 v[8:9], v[0:3], off sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: s_endpgm +; +; GISEL-LABEL: test_mfma_i32_32x32x32_i8: +; GISEL: ; %bb.0: +; GISEL-NEXT: s_load_dwordx8 s[20:27], s[0:1], 0x24 +; GISEL-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x64 +; GISEL-NEXT: v_mov_b64_e32 v[8:9], 0 +; GISEL-NEXT: v_mov_b64_e32 v[10:11], 48 +; GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[20:21] +; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[24:25] +; GISEL-NEXT: v_accvgpr_write_b32 a31, s19 +; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[22:23] +; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[26:27] +; GISEL-NEXT: v_accvgpr_write_b32 a30, s18 +; GISEL-NEXT: v_accvgpr_write_b32 a29, s17 +; GISEL-NEXT: v_accvgpr_write_b32 a28, s16 +; GISEL-NEXT: v_accvgpr_write_b32 a27, s15 +; GISEL-NEXT: v_accvgpr_write_b32 a26, s14 +; GISEL-NEXT: v_accvgpr_write_b32 a25, s13 +; GISEL-NEXT: v_accvgpr_write_b32 a24, s12 +; GISEL-NEXT: v_accvgpr_write_b32 a23, s11 +; GISEL-NEXT: v_accvgpr_write_b32 a22, s10 +; GISEL-NEXT: v_accvgpr_write_b32 a21, s9 +; GISEL-NEXT: v_accvgpr_write_b32 a20, s8 +; GISEL-NEXT: v_accvgpr_write_b32 a19, s7 +; GISEL-NEXT: v_accvgpr_write_b32 a18, s6 +; GISEL-NEXT: v_accvgpr_write_b32 a17, s5 +; GISEL-NEXT: v_accvgpr_write_b32 a16, s4 +; GISEL-NEXT: s_nop 1 +; GISEL-NEXT: v_mfma_i32_32x32x32_i8 a[0:15], v[0:3], v[4:7], a[16:31] +; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5] +; GISEL-NEXT: v_mov_b64_e32 v[4:5], 16 +; GISEL-NEXT: v_mov_b64_e32 v[6:7], 32 +; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[6:7] +; GISEL-NEXT: s_nop 7 +; GISEL-NEXT: s_nop 6 +; GISEL-NEXT: global_store_dwordx4 v[8:9], a[0:3], off sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: global_store_dwordx4 v[4:5], a[4:7], off sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: global_store_dwordx4 v[6:7], a[8:11], off sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: global_store_dwordx4 v[10:11], a[12:15], off sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: global_store_dwordx4 v[8:9], v[0:3], off sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: s_nop 0 +; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9] +; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11] +; GISEL-NEXT: global_store_dwordx4 v[4:5], v[0:3], off sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: s_nop 0 +; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[12:13] +; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[14:15] +; GISEL-NEXT: global_store_dwordx4 v[6:7], v[0:3], off sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: s_nop 0 +; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[16:17] +; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[18:19] +; GISEL-NEXT: global_store_dwordx4 v[10:11], v[0:3], off sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: s_endpgm + %result = call <16 x i32> @llvm.amdgcn.mfma.i32.32x32x32.i8(<4 x i32> %arg0, <4 x i32> %arg1, <16 x i32> %arg2, i32 0, i32 0, i32 0) + store volatile <16 x i32> %result, ptr addrspace(1) null + store volatile <16 x i32> %arg2, ptr addrspace(1) null + ret void +} + +define amdgpu_kernel void @test_mfma_i32_32x32x32_i8__flags(<4 x i32> %arg0, <4 x i32> %arg1, <16 x i32> %arg2) #1 { +; SDAG-LABEL: test_mfma_i32_32x32x32_i8__flags: +; SDAG: ; %bb.0: +; SDAG-NEXT: s_load_dwordx8 s[20:27], s[0:1], 0x24 +; SDAG-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x64 +; SDAG-NEXT: v_mov_b64_e32 v[8:9], 16 +; SDAG-NEXT: v_mov_b64_e32 v[10:11], 0 +; SDAG-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-NEXT: v_mov_b32_e32 v0, s20 +; SDAG-NEXT: v_accvgpr_write_b32 a31, s19 +; SDAG-NEXT: v_mov_b32_e32 v1, s21 +; SDAG-NEXT: v_mov_b32_e32 v2, s22 +; SDAG-NEXT: v_mov_b32_e32 v3, s23 +; SDAG-NEXT: v_mov_b32_e32 v4, s24 +; SDAG-NEXT: v_mov_b32_e32 v5, s25 +; SDAG-NEXT: v_mov_b32_e32 v6, s26 +; SDAG-NEXT: v_mov_b32_e32 v7, s27 +; SDAG-NEXT: v_accvgpr_write_b32 a30, s18 +; SDAG-NEXT: v_accvgpr_write_b32 a29, s17 +; SDAG-NEXT: v_accvgpr_write_b32 a28, s16 +; SDAG-NEXT: v_accvgpr_write_b32 a27, s15 +; SDAG-NEXT: v_accvgpr_write_b32 a26, s14 +; SDAG-NEXT: v_accvgpr_write_b32 a25, s13 +; SDAG-NEXT: v_accvgpr_write_b32 a24, s12 +; SDAG-NEXT: v_accvgpr_write_b32 a23, s11 +; SDAG-NEXT: v_accvgpr_write_b32 a22, s10 +; SDAG-NEXT: v_accvgpr_write_b32 a21, s9 +; SDAG-NEXT: v_accvgpr_write_b32 a20, s8 +; SDAG-NEXT: v_accvgpr_write_b32 a19, s7 +; SDAG-NEXT: v_accvgpr_write_b32 a18, s6 +; SDAG-NEXT: v_accvgpr_write_b32 a17, s5 +; SDAG-NEXT: v_accvgpr_write_b32 a16, s4 +; SDAG-NEXT: s_nop 1 +; SDAG-NEXT: v_mfma_i32_32x32x32_i8 a[0:15], v[0:3], v[4:7], a[16:31] cbsz:2 abid:3 blgp:1 +; SDAG-NEXT: v_mov_b64_e32 v[4:5], 48 +; SDAG-NEXT: v_mov_b64_e32 v[6:7], 32 +; SDAG-NEXT: v_mov_b32_e32 v0, s12 +; SDAG-NEXT: v_mov_b32_e32 v1, s13 +; SDAG-NEXT: v_mov_b32_e32 v2, s14 +; SDAG-NEXT: v_mov_b32_e32 v3, s15 +; SDAG-NEXT: s_nop 7 +; SDAG-NEXT: s_nop 4 +; SDAG-NEXT: global_store_dwordx4 v[4:5], a[12:15], off sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: global_store_dwordx4 v[6:7], a[8:11], off sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: global_store_dwordx4 v[8:9], a[4:7], off sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: global_store_dwordx4 v[10:11], a[0:3], off sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: global_store_dwordx4 v[6:7], v[0:3], off sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: s_nop 0 +; SDAG-NEXT: v_mov_b32_e32 v0, s16 +; SDAG-NEXT: v_mov_b32_e32 v1, s17 +; SDAG-NEXT: v_mov_b32_e32 v2, s18 +; SDAG-NEXT: v_mov_b32_e32 v3, s19 +; SDAG-NEXT: global_store_dwordx4 v[4:5], v[0:3], off sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: s_nop 0 +; SDAG-NEXT: v_mov_b32_e32 v0, s4 +; SDAG-NEXT: v_mov_b32_e32 v1, s5 +; SDAG-NEXT: v_mov_b32_e32 v2, s6 +; SDAG-NEXT: v_mov_b32_e32 v3, s7 +; SDAG-NEXT: global_store_dwordx4 v[10:11], v[0:3], off sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: s_nop 0 +; SDAG-NEXT: v_mov_b32_e32 v0, s8 +; SDAG-NEXT: v_mov_b32_e32 v1, s9 +; SDAG-NEXT: v_mov_b32_e32 v2, s10 +; SDAG-NEXT: v_mov_b32_e32 v3, s11 +; SDAG-NEXT: global_store_dwordx4 v[8:9], v[0:3], off sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: s_endpgm +; +; GISEL-LABEL: test_mfma_i32_32x32x32_i8__flags: +; GISEL: ; %bb.0: +; GISEL-NEXT: s_load_dwordx8 s[20:27], s[0:1], 0x24 +; GISEL-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x64 +; GISEL-NEXT: v_mov_b64_e32 v[8:9], 0 +; GISEL-NEXT: v_mov_b64_e32 v[10:11], 48 +; GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[20:21] +; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[24:25] +; GISEL-NEXT: v_accvgpr_write_b32 a31, s19 +; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[22:23] +; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[26:27] +; GISEL-NEXT: v_accvgpr_write_b32 a30, s18 +; GISEL-NEXT: v_accvgpr_write_b32 a29, s17 +; GISEL-NEXT: v_accvgpr_write_b32 a28, s16 +; GISEL-NEXT: v_accvgpr_write_b32 a27, s15 +; GISEL-NEXT: v_accvgpr_write_b32 a26, s14 +; GISEL-NEXT: v_accvgpr_write_b32 a25, s13 +; GISEL-NEXT: v_accvgpr_write_b32 a24, s12 +; GISEL-NEXT: v_accvgpr_write_b32 a23, s11 +; GISEL-NEXT: v_accvgpr_write_b32 a22, s10 +; GISEL-NEXT: v_accvgpr_write_b32 a21, s9 +; GISEL-NEXT: v_accvgpr_write_b32 a20, s8 +; GISEL-NEXT: v_accvgpr_write_b32 a19, s7 +; GISEL-NEXT: v_accvgpr_write_b32 a18, s6 +; GISEL-NEXT: v_accvgpr_write_b32 a17, s5 +; GISEL-NEXT: v_accvgpr_write_b32 a16, s4 +; GISEL-NEXT: s_nop 1 +; GISEL-NEXT: v_mfma_i32_32x32x32_i8 a[0:15], v[0:3], v[4:7], a[16:31] cbsz:2 abid:3 blgp:1 +; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5] +; GISEL-NEXT: v_mov_b64_e32 v[4:5], 16 +; GISEL-NEXT: v_mov_b64_e32 v[6:7], 32 +; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[6:7] +; GISEL-NEXT: s_nop 7 +; GISEL-NEXT: s_nop 6 +; GISEL-NEXT: global_store_dwordx4 v[8:9], a[0:3], off sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: global_store_dwordx4 v[4:5], a[4:7], off sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: global_store_dwordx4 v[6:7], a[8:11], off sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: global_store_dwordx4 v[10:11], a[12:15], off sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: global_store_dwordx4 v[8:9], v[0:3], off sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: s_nop 0 +; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9] +; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11] +; GISEL-NEXT: global_store_dwordx4 v[4:5], v[0:3], off sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: s_nop 0 +; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[12:13] +; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[14:15] +; GISEL-NEXT: global_store_dwordx4 v[6:7], v[0:3], off sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: s_nop 0 +; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[16:17] +; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[18:19] +; GISEL-NEXT: global_store_dwordx4 v[10:11], v[0:3], off sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: s_endpgm + %result = call <16 x i32> @llvm.amdgcn.mfma.i32.32x32x32.i8(<4 x i32> %arg0, <4 x i32> %arg1, <16 x i32> %arg2, i32 2, i32 3, i32 1) + store volatile <16 x i32> %result, ptr addrspace(1) null + store volatile <16 x i32> %arg2, ptr addrspace(1) null + ret void +} + +define <16 x i32> @test_mfma_i32_32x32x32_i8__mac(<4 x i32> %arg0, <4 x i32> %arg1, <16 x i32> %arg2) { +; GCN-LABEL: test_mfma_i32_32x32x32_i8__mac: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_accvgpr_write_b32 a0, v8 +; GCN-NEXT: v_accvgpr_write_b32 a1, v9 +; GCN-NEXT: v_accvgpr_write_b32 a2, v10 +; GCN-NEXT: v_accvgpr_write_b32 a3, v11 +; GCN-NEXT: v_accvgpr_write_b32 a4, v12 +; GCN-NEXT: v_accvgpr_write_b32 a5, v13 +; GCN-NEXT: v_accvgpr_write_b32 a6, v14 +; GCN-NEXT: v_accvgpr_write_b32 a7, v15 +; GCN-NEXT: v_accvgpr_write_b32 a8, v16 +; GCN-NEXT: v_accvgpr_write_b32 a9, v17 +; GCN-NEXT: v_accvgpr_write_b32 a10, v18 +; GCN-NEXT: v_accvgpr_write_b32 a11, v19 +; GCN-NEXT: v_accvgpr_write_b32 a12, v20 +; GCN-NEXT: v_accvgpr_write_b32 a13, v21 +; GCN-NEXT: v_accvgpr_write_b32 a14, v22 +; GCN-NEXT: v_accvgpr_write_b32 a15, v23 +; GCN-NEXT: s_nop 1 +; GCN-NEXT: v_mfma_i32_32x32x32_i8 a[0:15], v[0:3], v[4:7], a[0:15] +; GCN-NEXT: s_nop 3 +; GCN-NEXT: v_accvgpr_read_b32 v0, a0 +; GCN-NEXT: v_accvgpr_read_b32 v1, a1 +; GCN-NEXT: v_accvgpr_read_b32 v2, a2 +; GCN-NEXT: v_accvgpr_read_b32 v3, a3 +; GCN-NEXT: v_accvgpr_read_b32 v4, a4 +; GCN-NEXT: v_accvgpr_read_b32 v5, a5 +; GCN-NEXT: v_accvgpr_read_b32 v6, a6 +; GCN-NEXT: v_accvgpr_read_b32 v7, a7 +; GCN-NEXT: v_accvgpr_read_b32 v8, a8 +; GCN-NEXT: v_accvgpr_read_b32 v9, a9 +; GCN-NEXT: v_accvgpr_read_b32 v10, a10 +; GCN-NEXT: v_accvgpr_read_b32 v11, a11 +; GCN-NEXT: v_accvgpr_read_b32 v12, a12 +; GCN-NEXT: v_accvgpr_read_b32 v13, a13 +; GCN-NEXT: v_accvgpr_read_b32 v14, a14 +; GCN-NEXT: v_accvgpr_read_b32 v15, a15 +; GCN-NEXT: s_setpc_b64 s[30:31] + %result = call <16 x i32> @llvm.amdgcn.mfma.i32.32x32x32.i8(<4 x i32> %arg0, <4 x i32> %arg1, <16 x i32> %arg2, i32 0, i32 0, i32 0) + ret <16 x i32> %result +} + +define <16 x i32> @test_mfma_i32_32x32x32_i8__mac__flags(<4 x i32> %arg0, <4 x i32> %arg1, <16 x i32> %arg2) { +; GCN-LABEL: test_mfma_i32_32x32x32_i8__mac__flags: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_accvgpr_write_b32 a0, v8 +; GCN-NEXT: v_accvgpr_write_b32 a1, v9 +; GCN-NEXT: v_accvgpr_write_b32 a2, v10 +; GCN-NEXT: v_accvgpr_write_b32 a3, v11 +; GCN-NEXT: v_accvgpr_write_b32 a4, v12 +; GCN-NEXT: v_accvgpr_write_b32 a5, v13 +; GCN-NEXT: v_accvgpr_write_b32 a6, v14 +; GCN-NEXT: v_accvgpr_write_b32 a7, v15 +; GCN-NEXT: v_accvgpr_write_b32 a8, v16 +; GCN-NEXT: v_accvgpr_write_b32 a9, v17 +; GCN-NEXT: v_accvgpr_write_b32 a10, v18 +; GCN-NEXT: v_accvgpr_write_b32 a11, v19 +; GCN-NEXT: v_accvgpr_write_b32 a12, v20 +; GCN-NEXT: v_accvgpr_write_b32 a13, v21 +; GCN-NEXT: v_accvgpr_write_b32 a14, v22 +; GCN-NEXT: v_accvgpr_write_b32 a15, v23 +; GCN-NEXT: s_nop 1 +; GCN-NEXT: v_mfma_i32_32x32x32_i8 a[0:15], v[0:3], v[4:7], a[0:15] cbsz:1 abid:1 blgp:1 +; GCN-NEXT: s_nop 3 +; GCN-NEXT: v_accvgpr_read_b32 v0, a0 +; GCN-NEXT: v_accvgpr_read_b32 v1, a1 +; GCN-NEXT: v_accvgpr_read_b32 v2, a2 +; GCN-NEXT: v_accvgpr_read_b32 v3, a3 +; GCN-NEXT: v_accvgpr_read_b32 v4, a4 +; GCN-NEXT: v_accvgpr_read_b32 v5, a5 +; GCN-NEXT: v_accvgpr_read_b32 v6, a6 +; GCN-NEXT: v_accvgpr_read_b32 v7, a7 +; GCN-NEXT: v_accvgpr_read_b32 v8, a8 +; GCN-NEXT: v_accvgpr_read_b32 v9, a9 +; GCN-NEXT: v_accvgpr_read_b32 v10, a10 +; GCN-NEXT: v_accvgpr_read_b32 v11, a11 +; GCN-NEXT: v_accvgpr_read_b32 v12, a12 +; GCN-NEXT: v_accvgpr_read_b32 v13, a13 +; GCN-NEXT: v_accvgpr_read_b32 v14, a14 +; GCN-NEXT: v_accvgpr_read_b32 v15, a15 +; GCN-NEXT: s_setpc_b64 s[30:31] + %result = call <16 x i32> @llvm.amdgcn.mfma.i32.32x32x32.i8(<4 x i32> %arg0, <4 x i32> %arg1, <16 x i32> %arg2, i32 1, i32 1, i32 1) + ret <16 x i32> %result +} + +define amdgpu_kernel void @test_mfma_i32_32x32x32_i8__vgprcd(<4 x i32> %arg0, <4 x i32> %arg1, <16 x i32> %arg2, ptr addrspace(1) %out) #0 { +; SDAG-LABEL: test_mfma_i32_32x32x32_i8__vgprcd: +; SDAG: ; %bb.0: +; SDAG-NEXT: s_load_dwordx8 s[16:23], s[0:1], 0x24 +; SDAG-NEXT: v_mov_b32_e32 v40, 0 +; SDAG-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-NEXT: v_mov_b32_e32 v32, s16 +; SDAG-NEXT: v_mov_b32_e32 v33, s17 +; SDAG-NEXT: v_mov_b32_e32 v34, s18 +; SDAG-NEXT: v_mov_b32_e32 v35, s19 +; SDAG-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x64 +; SDAG-NEXT: v_mov_b32_e32 v36, s20 +; SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xa4 +; SDAG-NEXT: v_mov_b32_e32 v37, s21 +; SDAG-NEXT: v_mov_b32_e32 v38, s22 +; SDAG-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-NEXT: v_mov_b64_e32 v[30:31], s[18:19] +; SDAG-NEXT: v_mov_b32_e32 v39, s23 +; SDAG-NEXT: v_mov_b64_e32 v[28:29], s[16:17] +; SDAG-NEXT: v_mov_b64_e32 v[26:27], s[14:15] +; SDAG-NEXT: v_mov_b64_e32 v[24:25], s[12:13] +; SDAG-NEXT: v_mov_b64_e32 v[22:23], s[10:11] +; SDAG-NEXT: v_mov_b64_e32 v[20:21], s[8:9] +; SDAG-NEXT: v_mov_b64_e32 v[18:19], s[6:7] +; SDAG-NEXT: v_mov_b64_e32 v[16:17], s[4:5] +; SDAG-NEXT: s_nop 1 +; SDAG-NEXT: v_mfma_i32_32x32x32_i8 v[0:15], v[32:35], v[36:39], v[16:31] +; SDAG-NEXT: s_nop 7 +; SDAG-NEXT: s_nop 6 +; SDAG-NEXT: v_mov_b32_e32 v16, s16 +; SDAG-NEXT: v_mov_b32_e32 v17, s17 +; SDAG-NEXT: v_mov_b32_e32 v18, s18 +; SDAG-NEXT: v_mov_b32_e32 v19, s19 +; SDAG-NEXT: global_store_dwordx4 v40, v[16:19], s[0:1] offset:48 sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: s_nop 0 +; SDAG-NEXT: v_mov_b32_e32 v16, s12 +; SDAG-NEXT: v_mov_b32_e32 v17, s13 +; SDAG-NEXT: v_mov_b32_e32 v18, s14 +; SDAG-NEXT: v_mov_b32_e32 v19, s15 +; SDAG-NEXT: global_store_dwordx4 v40, v[16:19], s[0:1] offset:32 sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: s_nop 0 +; SDAG-NEXT: v_mov_b32_e32 v16, s8 +; SDAG-NEXT: v_mov_b32_e32 v17, s9 +; SDAG-NEXT: v_mov_b32_e32 v18, s10 +; SDAG-NEXT: v_mov_b32_e32 v19, s11 +; SDAG-NEXT: global_store_dwordx4 v40, v[16:19], s[0:1] offset:16 sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: s_nop 0 +; SDAG-NEXT: v_mov_b32_e32 v16, s4 +; SDAG-NEXT: v_mov_b32_e32 v17, s5 +; SDAG-NEXT: v_mov_b32_e32 v18, s6 +; SDAG-NEXT: v_mov_b32_e32 v19, s7 +; SDAG-NEXT: global_store_dwordx4 v40, v[16:19], s[0:1] sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: global_store_dwordx4 v40, v[8:11], s[0:1] offset:32 sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: global_store_dwordx4 v40, v[12:15], s[0:1] offset:48 sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: global_store_dwordx4 v40, v[0:3], s[0:1] sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: global_store_dwordx4 v40, v[4:7], s[0:1] offset:16 sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: s_endpgm +; +; GISEL-LABEL: test_mfma_i32_32x32x32_i8__vgprcd: +; GISEL: ; %bb.0: +; GISEL-NEXT: s_load_dwordx8 s[20:27], s[0:1], 0x24 +; GISEL-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x64 +; GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xa4 +; GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[22:23] +; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[26:27] +; GISEL-NEXT: v_mov_b64_e32 v[30:31], s[18:19] +; GISEL-NEXT: v_mov_b64_e32 v[32:33], s[20:21] +; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[24:25] +; GISEL-NEXT: v_mov_b64_e32 v[28:29], s[16:17] +; GISEL-NEXT: v_mov_b64_e32 v[26:27], s[14:15] +; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[12:13] +; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[10:11] +; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[8:9] +; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[6:7] +; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[4:5] +; GISEL-NEXT: s_nop 1 +; GISEL-NEXT: v_mfma_i32_32x32x32_i8 v[0:15], v[32:35], v[36:39], v[16:31] +; GISEL-NEXT: s_nop 7 +; GISEL-NEXT: s_nop 6 +; GISEL-NEXT: v_mov_b32_e32 v20, 0 +; GISEL-NEXT: global_store_dwordx4 v20, v[16:19], s[2:3] sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: s_nop 0 +; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[10:11] +; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[8:9] +; GISEL-NEXT: global_store_dwordx4 v20, v[16:19], s[2:3] offset:16 sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: s_nop 0 +; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[14:15] +; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[12:13] +; GISEL-NEXT: global_store_dwordx4 v20, v[16:19], s[2:3] offset:32 sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: s_nop 0 +; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[16:17] +; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[18:19] +; GISEL-NEXT: global_store_dwordx4 v20, v[16:19], s[2:3] offset:48 sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: global_store_dwordx4 v20, v[0:3], s[2:3] sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: global_store_dwordx4 v20, v[4:7], s[2:3] offset:16 sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: global_store_dwordx4 v20, v[8:11], s[2:3] offset:32 sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: global_store_dwordx4 v20, v[12:15], s[2:3] offset:48 sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: s_endpgm + %result = call <16 x i32> @llvm.amdgcn.mfma.i32.32x32x32.i8(<4 x i32> %arg0, <4 x i32> %arg1, <16 x i32> %arg2, i32 0, i32 0, i32 0) + store volatile <16 x i32> %arg2, ptr addrspace(1) %out + store volatile <16 x i32> %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_kernel void @test_mfma_i32_32x32x32_i8__vgprcd__flags(<4 x i32> %arg0, <4 x i32> %arg1, <16 x i32> %arg2, ptr addrspace(1) %out) #0 { +; SDAG-LABEL: test_mfma_i32_32x32x32_i8__vgprcd__flags: +; SDAG: ; %bb.0: +; SDAG-NEXT: s_load_dwordx8 s[16:23], s[0:1], 0x24 +; SDAG-NEXT: v_mov_b32_e32 v40, 0 +; SDAG-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-NEXT: v_mov_b32_e32 v32, s16 +; SDAG-NEXT: v_mov_b32_e32 v33, s17 +; SDAG-NEXT: v_mov_b32_e32 v34, s18 +; SDAG-NEXT: v_mov_b32_e32 v35, s19 +; SDAG-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x64 +; SDAG-NEXT: v_mov_b32_e32 v36, s20 +; SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xa4 +; SDAG-NEXT: v_mov_b32_e32 v37, s21 +; SDAG-NEXT: v_mov_b32_e32 v38, s22 +; SDAG-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-NEXT: v_mov_b64_e32 v[30:31], s[18:19] +; SDAG-NEXT: v_mov_b32_e32 v39, s23 +; SDAG-NEXT: v_mov_b64_e32 v[28:29], s[16:17] +; SDAG-NEXT: v_mov_b64_e32 v[26:27], s[14:15] +; SDAG-NEXT: v_mov_b64_e32 v[24:25], s[12:13] +; SDAG-NEXT: v_mov_b64_e32 v[22:23], s[10:11] +; SDAG-NEXT: v_mov_b64_e32 v[20:21], s[8:9] +; SDAG-NEXT: v_mov_b64_e32 v[18:19], s[6:7] +; SDAG-NEXT: v_mov_b64_e32 v[16:17], s[4:5] +; SDAG-NEXT: s_nop 1 +; SDAG-NEXT: v_mfma_i32_32x32x32_i8 v[0:15], v[32:35], v[36:39], v[16:31] cbsz:1 abid:2 blgp:3 +; SDAG-NEXT: s_nop 7 +; SDAG-NEXT: s_nop 6 +; SDAG-NEXT: v_mov_b32_e32 v16, s16 +; SDAG-NEXT: v_mov_b32_e32 v17, s17 +; SDAG-NEXT: v_mov_b32_e32 v18, s18 +; SDAG-NEXT: v_mov_b32_e32 v19, s19 +; SDAG-NEXT: global_store_dwordx4 v40, v[16:19], s[0:1] offset:48 sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: s_nop 0 +; SDAG-NEXT: v_mov_b32_e32 v16, s12 +; SDAG-NEXT: v_mov_b32_e32 v17, s13 +; SDAG-NEXT: v_mov_b32_e32 v18, s14 +; SDAG-NEXT: v_mov_b32_e32 v19, s15 +; SDAG-NEXT: global_store_dwordx4 v40, v[16:19], s[0:1] offset:32 sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: s_nop 0 +; SDAG-NEXT: v_mov_b32_e32 v16, s8 +; SDAG-NEXT: v_mov_b32_e32 v17, s9 +; SDAG-NEXT: v_mov_b32_e32 v18, s10 +; SDAG-NEXT: v_mov_b32_e32 v19, s11 +; SDAG-NEXT: global_store_dwordx4 v40, v[16:19], s[0:1] offset:16 sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: s_nop 0 +; SDAG-NEXT: v_mov_b32_e32 v16, s4 +; SDAG-NEXT: v_mov_b32_e32 v17, s5 +; SDAG-NEXT: v_mov_b32_e32 v18, s6 +; SDAG-NEXT: v_mov_b32_e32 v19, s7 +; SDAG-NEXT: global_store_dwordx4 v40, v[16:19], s[0:1] sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: global_store_dwordx4 v40, v[8:11], s[0:1] offset:32 sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: global_store_dwordx4 v40, v[12:15], s[0:1] offset:48 sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: global_store_dwordx4 v40, v[0:3], s[0:1] sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: global_store_dwordx4 v40, v[4:7], s[0:1] offset:16 sc0 sc1 +; SDAG-NEXT: s_waitcnt vmcnt(0) +; SDAG-NEXT: s_endpgm +; +; GISEL-LABEL: test_mfma_i32_32x32x32_i8__vgprcd__flags: +; GISEL: ; %bb.0: +; GISEL-NEXT: s_load_dwordx8 s[20:27], s[0:1], 0x24 +; GISEL-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x64 +; GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xa4 +; GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[22:23] +; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[26:27] +; GISEL-NEXT: v_mov_b64_e32 v[30:31], s[18:19] +; GISEL-NEXT: v_mov_b64_e32 v[32:33], s[20:21] +; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[24:25] +; GISEL-NEXT: v_mov_b64_e32 v[28:29], s[16:17] +; GISEL-NEXT: v_mov_b64_e32 v[26:27], s[14:15] +; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[12:13] +; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[10:11] +; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[8:9] +; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[6:7] +; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[4:5] +; GISEL-NEXT: s_nop 1 +; GISEL-NEXT: v_mfma_i32_32x32x32_i8 v[0:15], v[32:35], v[36:39], v[16:31] cbsz:1 abid:2 blgp:3 +; GISEL-NEXT: s_nop 7 +; GISEL-NEXT: s_nop 6 +; GISEL-NEXT: v_mov_b32_e32 v20, 0 +; GISEL-NEXT: global_store_dwordx4 v20, v[16:19], s[2:3] sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: s_nop 0 +; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[10:11] +; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[8:9] +; GISEL-NEXT: global_store_dwordx4 v20, v[16:19], s[2:3] offset:16 sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: s_nop 0 +; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[14:15] +; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[12:13] +; GISEL-NEXT: global_store_dwordx4 v20, v[16:19], s[2:3] offset:32 sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: s_nop 0 +; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[16:17] +; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[18:19] +; GISEL-NEXT: global_store_dwordx4 v20, v[16:19], s[2:3] offset:48 sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: global_store_dwordx4 v20, v[0:3], s[2:3] sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: global_store_dwordx4 v20, v[4:7], s[2:3] offset:16 sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: global_store_dwordx4 v20, v[8:11], s[2:3] offset:32 sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: global_store_dwordx4 v20, v[12:15], s[2:3] offset:48 sc0 sc1 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: s_endpgm + %result = call <16 x i32> @llvm.amdgcn.mfma.i32.32x32x32.i8(<4 x i32> %arg0, <4 x i32> %arg1, <16 x i32> %arg2, i32 1, i32 2, i32 3) + store volatile <16 x i32> %arg2, ptr addrspace(1) %out + store volatile <16 x i32> %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_kernel void @test_mfma_i32_32x32x32_i8__vgprcd_mac(<4 x i32> %arg0, <4 x i32> %arg1, <16 x i32> %arg2, ptr addrspace(1) %out) #0 { +; SDAG-LABEL: test_mfma_i32_32x32x32_i8__vgprcd_mac: +; SDAG: ; %bb.0: +; SDAG-NEXT: s_load_dwordx8 s[16:23], s[0:1], 0x24 +; SDAG-NEXT: v_mov_b32_e32 v24, 0 +; SDAG-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-NEXT: v_mov_b32_e32 v16, s16 +; SDAG-NEXT: v_mov_b32_e32 v17, s17 +; SDAG-NEXT: v_mov_b32_e32 v18, s18 +; SDAG-NEXT: v_mov_b32_e32 v19, s19 +; SDAG-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x64 +; SDAG-NEXT: v_mov_b32_e32 v20, s20 +; SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xa4 +; SDAG-NEXT: v_mov_b32_e32 v21, s21 +; SDAG-NEXT: v_mov_b32_e32 v22, s22 +; SDAG-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[4:5] +; SDAG-NEXT: v_mov_b32_e32 v23, s23 +; SDAG-NEXT: v_mov_b64_e32 v[2:3], s[6:7] +; SDAG-NEXT: v_mov_b64_e32 v[4:5], s[8:9] +; SDAG-NEXT: v_mov_b64_e32 v[6:7], s[10:11] +; SDAG-NEXT: v_mov_b64_e32 v[8:9], s[12:13] +; SDAG-NEXT: v_mov_b64_e32 v[10:11], s[14:15] +; SDAG-NEXT: v_mov_b64_e32 v[12:13], s[16:17] +; SDAG-NEXT: v_mov_b64_e32 v[14:15], s[18:19] +; SDAG-NEXT: s_nop 1 +; SDAG-NEXT: v_mfma_i32_32x32x32_i8 v[0:15], v[16:19], v[20:23], v[0:15] +; SDAG-NEXT: s_nop 7 +; SDAG-NEXT: s_nop 7 +; SDAG-NEXT: s_nop 2 +; SDAG-NEXT: global_store_dwordx4 v24, v[12:15], s[0:1] offset:48 +; SDAG-NEXT: global_store_dwordx4 v24, v[8:11], s[0:1] offset:32 +; SDAG-NEXT: global_store_dwordx4 v24, v[4:7], s[0:1] offset:16 +; SDAG-NEXT: global_store_dwordx4 v24, v[0:3], s[0:1] +; SDAG-NEXT: s_endpgm +; +; GISEL-LABEL: test_mfma_i32_32x32x32_i8__vgprcd_mac: +; GISEL: ; %bb.0: +; GISEL-NEXT: s_load_dwordx8 s[20:27], s[0:1], 0x24 +; GISEL-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x64 +; GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xa4 +; GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21] +; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[24:25] +; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5] +; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23] +; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[26:27] +; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[6:7] +; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[8:9] +; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[10:11] +; GISEL-NEXT: v_mov_b64_e32 v[8:9], s[12:13] +; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[14:15] +; GISEL-NEXT: v_mov_b64_e32 v[12:13], s[16:17] +; GISEL-NEXT: v_mov_b64_e32 v[14:15], s[18:19] +; GISEL-NEXT: s_nop 1 +; GISEL-NEXT: v_mfma_i32_32x32x32_i8 v[0:15], v[16:19], v[20:23], v[0:15] +; GISEL-NEXT: v_mov_b32_e32 v16, 0 +; GISEL-NEXT: s_nop 7 +; GISEL-NEXT: s_nop 7 +; GISEL-NEXT: s_nop 1 +; GISEL-NEXT: global_store_dwordx4 v16, v[0:3], s[2:3] +; GISEL-NEXT: global_store_dwordx4 v16, v[4:7], s[2:3] offset:16 +; GISEL-NEXT: global_store_dwordx4 v16, v[8:11], s[2:3] offset:32 +; GISEL-NEXT: global_store_dwordx4 v16, v[12:15], s[2:3] offset:48 +; GISEL-NEXT: s_endpgm + %result = call <16 x i32> @llvm.amdgcn.mfma.i32.32x32x32.i8(<4 x i32> %arg0, <4 x i32> %arg1, <16 x i32> %arg2, i32 0, i32 0, i32 0) + store <16 x i32> %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_kernel void @test_mfma_i32_32x32x32_i8__vgprcd_mac_flags(<4 x i32> %arg0, <4 x i32> %arg1, <16 x i32> %arg2, ptr addrspace(1) %out) #0 { +; SDAG-LABEL: test_mfma_i32_32x32x32_i8__vgprcd_mac_flags: +; SDAG: ; %bb.0: +; SDAG-NEXT: s_load_dwordx8 s[16:23], s[0:1], 0x24 +; SDAG-NEXT: v_mov_b32_e32 v24, 0 +; SDAG-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-NEXT: v_mov_b32_e32 v16, s16 +; SDAG-NEXT: v_mov_b32_e32 v17, s17 +; SDAG-NEXT: v_mov_b32_e32 v18, s18 +; SDAG-NEXT: v_mov_b32_e32 v19, s19 +; SDAG-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x64 +; SDAG-NEXT: v_mov_b32_e32 v20, s20 +; SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xa4 +; SDAG-NEXT: v_mov_b32_e32 v21, s21 +; SDAG-NEXT: v_mov_b32_e32 v22, s22 +; SDAG-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[4:5] +; SDAG-NEXT: v_mov_b32_e32 v23, s23 +; SDAG-NEXT: v_mov_b64_e32 v[2:3], s[6:7] +; SDAG-NEXT: v_mov_b64_e32 v[4:5], s[8:9] +; SDAG-NEXT: v_mov_b64_e32 v[6:7], s[10:11] +; SDAG-NEXT: v_mov_b64_e32 v[8:9], s[12:13] +; SDAG-NEXT: v_mov_b64_e32 v[10:11], s[14:15] +; SDAG-NEXT: v_mov_b64_e32 v[12:13], s[16:17] +; SDAG-NEXT: v_mov_b64_e32 v[14:15], s[18:19] +; SDAG-NEXT: s_nop 1 +; SDAG-NEXT: v_mfma_i32_32x32x32_i8 v[0:15], v[16:19], v[20:23], v[0:15] cbsz:3 abid:2 blgp:1 +; SDAG-NEXT: s_nop 7 +; SDAG-NEXT: s_nop 7 +; SDAG-NEXT: s_nop 2 +; SDAG-NEXT: global_store_dwordx4 v24, v[12:15], s[0:1] offset:48 +; SDAG-NEXT: global_store_dwordx4 v24, v[8:11], s[0:1] offset:32 +; SDAG-NEXT: global_store_dwordx4 v24, v[4:7], s[0:1] offset:16 +; SDAG-NEXT: global_store_dwordx4 v24, v[0:3], s[0:1] +; SDAG-NEXT: s_endpgm +; +; GISEL-LABEL: test_mfma_i32_32x32x32_i8__vgprcd_mac_flags: +; GISEL: ; %bb.0: +; GISEL-NEXT: s_load_dwordx8 s[20:27], s[0:1], 0x24 +; GISEL-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x64 +; GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xa4 +; GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21] +; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[24:25] +; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5] +; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23] +; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[26:27] +; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[6:7] +; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[8:9] +; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[10:11] +; GISEL-NEXT: v_mov_b64_e32 v[8:9], s[12:13] +; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[14:15] +; GISEL-NEXT: v_mov_b64_e32 v[12:13], s[16:17] +; GISEL-NEXT: v_mov_b64_e32 v[14:15], s[18:19] +; GISEL-NEXT: s_nop 1 +; GISEL-NEXT: v_mfma_i32_32x32x32_i8 v[0:15], v[16:19], v[20:23], v[0:15] cbsz:3 abid:2 blgp:1 +; GISEL-NEXT: v_mov_b32_e32 v16, 0 +; GISEL-NEXT: s_nop 7 +; GISEL-NEXT: s_nop 7 +; GISEL-NEXT: s_nop 1 +; GISEL-NEXT: global_store_dwordx4 v16, v[0:3], s[2:3] +; GISEL-NEXT: global_store_dwordx4 v16, v[4:7], s[2:3] offset:16 +; GISEL-NEXT: global_store_dwordx4 v16, v[8:11], s[2:3] offset:32 +; GISEL-NEXT: global_store_dwordx4 v16, v[12:15], s[2:3] offset:48 +; GISEL-NEXT: s_endpgm + %result = call <16 x i32> @llvm.amdgcn.mfma.i32.32x32x32.i8(<4 x i32> %arg0, <4 x i32> %arg1, <16 x i32> %arg2, i32 3, i32 2, i32 1) + store <16 x i32> %result, ptr addrspace(1) %out + ret void +} + attributes #0 = { "amdgpu-flat-work-group-size"="512,512" } attributes #1 = { "amdgpu-flat-work-group-size"="1,64" } diff --git a/llvm/test/MC/AMDGPU/mai-gfx950.s b/llvm/test/MC/AMDGPU/mai-gfx950.s index 3e9d3ef7fa1648..a2ea2ff6f68d0d 100644 --- a/llvm/test/MC/AMDGPU/mai-gfx950.s +++ b/llvm/test/MC/AMDGPU/mai-gfx950.s @@ -946,3 +946,51 @@ v_mfma_i32_16x16x64_i8 a[0:3], v[0:3], v[0:3], a[4:7] // GFX950: v_mfma_i32_16x16x64_i8 v[0:3], a[0:3], a[0:3], v[4:7] ; encoding: [0x00,0x00,0xb6,0xd3,0x00,0x01,0x12,0x1c] // ERR: :[[@LINE+1]]:{{[0-9]+}}: error: instruction not supported on this GPU v_mfma_i32_16x16x64_i8 v[0:3], a[0:3], a[0:3], v[4:7] + +//===----------------------------------------------------------------------===// +// v_mfma_i32_32x32x32_i8 +//===----------------------------------------------------------------------===// + +// GFX950: v_mfma_i32_32x32x32_i8 v[0:15], v[0:3], v[0:3], v[0:15] ; encoding: [0x00,0x00,0xb8,0xd3,0x00,0x01,0x02,0x04] +// ERR: :[[@LINE+1]]:{{[0-9]+}}: error: instruction not supported on this GPU +v_mfma_i32_32x32x32_i8 v[0:15], v[0:3], v[0:3], v[0:15] + +// GFX950: v_mfma_i32_32x32x32_i8 a[0:15], a[0:3], a[0:3], a[0:15] ; encoding: [0x00,0x80,0xb8,0xd3,0x00,0x01,0x02,0x1c] +// ERR: :[[@LINE+1]]:{{[0-9]+}}: error: instruction not supported on this GPU +v_mfma_i32_32x32x32_i8 a[0:15], a[0:3], a[0:3], a[0:15] + +// GFX950: v_mfma_i32_32x32x32_i8 v[0:15], v[0:3], v[0:3], v[0:15] ; encoding: [0x00,0x00,0xb8,0xd3,0x00,0x01,0x02,0x04] +// ERR: :[[@LINE+1]]:{{[0-9]+}}: error: instruction not supported on this GPU +v_mfma_i32_32x32x32i8 v[0:15], v[0:3], v[0:3], v[0:15] + +// GFX950: v_mfma_i32_32x32x32_i8 a[0:15], a[0:3], a[0:3], a[0:15] ; encoding: [0x00,0x80,0xb8,0xd3,0x00,0x01,0x02,0x1c] +// ERR: :[[@LINE+1]]:{{[0-9]+}}: error: instruction not supported on this GPU +v_mfma_i32_32x32x32i8 a[0:15], a[0:3], a[0:3], a[0:15] + +// GFX950: v_mfma_i32_32x32x32_i8 v[0:15], v[0:3], v[0:3], 1.0 ; encoding: [0x00,0x00,0xb8,0xd3,0x00,0x01,0xca,0x03] +// ERR: :[[@LINE+1]]:{{[0-9]+}}: error: instruction not supported on this GPU +v_mfma_i32_32x32x32_i8 v[0:15], v[0:3], v[0:3], 1.0 + +// GFX950: v_mfma_i32_32x32x32_i8 a[0:15], a[0:3], a[0:3], 1.0 ; encoding: [0x00,0x80,0xb8,0xd3,0x00,0x01,0xca,0x1b] +// ERR: :[[@LINE+1]]:{{[0-9]+}}: error: instruction not supported on this GPU +v_mfma_i32_32x32x32_i8 a[0:15], a[0:3], a[0:3], 1.0 + +// GFX950: v_mfma_i32_32x32x32_i8 v[0:15], v[0:3], v[0:3], v[0:15] blgp:5 ; encoding: [0x00,0x00,0xb8,0xd3,0x00,0x01,0x02,0xa4] +// ERR: :[[@LINE+1]]:{{[0-9]+}}: error: instruction not supported on this GPU +v_mfma_i32_32x32x32_i8 v[0:15], v[0:3], v[0:3], v[0:15] blgp:5 + +// GFX950: v_mfma_i32_32x32x32_i8 a[0:15], a[0:3], a[0:3], a[0:15] blgp:2 ; encoding: [0x00,0x80,0xb8,0xd3,0x00,0x01,0x02,0x5c] +// ERR: :[[@LINE+1]]:{{[0-9]+}}: error: instruction not supported on this GPU +v_mfma_i32_32x32x32_i8 a[0:15], a[0:3], a[0:3], a[0:15] blgp:2 + +// GFX950: v_mfma_i32_32x32x32_i8 v[0:15], v[0:3], v[0:3], v[0:15] cbsz:3 ; encoding: [0x00,0x03,0xb8,0xd3,0x00,0x01,0x02,0x04] +// ERR: :[[@LINE+1]]:{{[0-9]+}}: error: instruction not supported on this GPU +v_mfma_i32_32x32x32_i8 v[0:15], v[0:3], v[0:3], v[0:15] cbsz:3 + +// GFX950: v_mfma_i32_32x32x32_i8 v[0:15], v[0:3], v[0:3], v[0:15] abid:1 ; encoding: [0x00,0x08,0xb8,0xd3,0x00,0x01,0x02,0x04] +// ERR: :[[@LINE+1]]:{{[0-9]+}}: error: instruction not supported on this GPU +v_mfma_i32_32x32x32_i8 v[0:15], v[0:3], v[0:3], v[0:15] abid:1 + +// GFX950: v_mfma_i32_32x32x32_i8 a[0:15], a[0:3], a[0:3], a[0:15] cbsz:3 abid:1 ; encoding: [0x00,0x8b,0xb8,0xd3,0x00,0x01,0x02,0x1c] +// ERR: :[[@LINE+1]]:{{[0-9]+}}: error: instruction not supported on this GPU +v_mfma_i32_32x32x32_i8 a[0:15], a[0:3], a[0:3], a[0:15] cbsz:3 abid:1 diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx950_mai.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx950_mai.txt index 715a71919181f5..88bf255a0637aa 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx950_mai.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx950_mai.txt @@ -602,3 +602,31 @@ # GFX950: v_mfma_i32_16x16x64_i8 v[0:3], v[0:3], v[0:3], v[0:3] blgp:5 ; encoding: [0x00,0x00,0xb6,0xd3,0x00,0x01,0x02,0xa4] 0x00,0x00,0xb6,0xd3,0x00,0x01,0x02,0xa4 + + +# GFX950: v_mfma_i32_32x32x32_i8 a[0:15], a[0:3], a[0:3], 1.0 ; encoding: [0x00,0x80,0xb8,0xd3,0x00,0x01,0xca,0x1b] +0x00,0x80,0xb8,0xd3,0x00,0x01,0xca,0x1b + +# GFX950: v_mfma_i32_32x32x32_i8 a[0:15], a[0:3], a[0:3], a[0:15] ; encoding: [0x00,0x80,0xb8,0xd3,0x00,0x01,0x02,0x1c] +0x00,0x80,0xb8,0xd3,0x00,0x01,0x02,0x1c + +# GFX950: v_mfma_i32_32x32x32_i8 a[0:15], a[0:3], a[0:3], a[0:15] blgp:2 ; encoding: [0x00,0x80,0xb8,0xd3,0x00,0x01,0x02,0x5c] +0x00,0x80,0xb8,0xd3,0x00,0x01,0x02,0x5c + +# GFX950: v_mfma_i32_32x32x32_i8 a[0:15], a[0:3], a[0:3], a[0:15] cbsz:3 abid:1 ; encoding: [0x00,0x8b,0xb8,0xd3,0x00,0x01,0x02,0x1c] +0x00,0x8b,0xb8,0xd3,0x00,0x01,0x02,0x1c + +# GFX950: v_mfma_i32_32x32x32_i8 v[0:15], v[0:3], v[0:3], 1.0 ; encoding: [0x00,0x00,0xb8,0xd3,0x00,0x01,0xca,0x03] +0x00,0x00,0xb8,0xd3,0x00,0x01,0xca,0x03 + +# GFX950: v_mfma_i32_32x32x32_i8 v[0:15], v[0:3], v[0:3], v[0:15] ; encoding: [0x00,0x00,0xb8,0xd3,0x00,0x01,0x02,0x04] +0x00,0x00,0xb8,0xd3,0x00,0x01,0x02,0x04 + +# GFX950: v_mfma_i32_32x32x32_i8 v[0:15], v[0:3], v[0:3], v[0:15] abid:1 ; encoding: [0x00,0x08,0xb8,0xd3,0x00,0x01,0x02,0x04] +0x00,0x08,0xb8,0xd3,0x00,0x01,0x02,0x04 + +# GFX950: v_mfma_i32_32x32x32_i8 v[0:15], v[0:3], v[0:3], v[0:15] blgp:5 ; encoding: [0x00,0x00,0xb8,0xd3,0x00,0x01,0x02,0xa4] +0x00,0x00,0xb8,0xd3,0x00,0x01,0x02,0xa4 + +# GFX950: v_mfma_i32_32x32x32_i8 v[0:15], v[0:3], v[0:3], v[0:15] cbsz:3 ; encoding: [0x00,0x03,0xb8,0xd3,0x00,0x01,0x02,0x04] +0x00,0x03,0xb8,0xd3,0x00,0x01,0x02,0x04 diff --git a/llvm/test/tools/llvm-mca/AMDGPU/gfx950.s b/llvm/test/tools/llvm-mca/AMDGPU/gfx950.s index 5d5bb4eb55060e..760a20731e2166 100644 --- a/llvm/test/tools/llvm-mca/AMDGPU/gfx950.s +++ b/llvm/test/tools/llvm-mca/AMDGPU/gfx950.s @@ -1,9 +1,9 @@ # RUN: llvm-mca -mtriple=amdgcn -mcpu=gfx950 --timeline --iterations=1 --timeline-max-cycles=0 < %s | FileCheck %s # CHECK: Iterations: 1 -# CHECK: Instructions: 11 -# CHECK: Total Cycles: 46 -# CHECK: Total uOps: 11 +# CHECK: Instructions: 13 +# CHECK: Total Cycles: 48 +# CHECK: Total uOps: 13 v_mfma_ld_scale_b32 v0, v0 v_mfma_f32_16x16x128_f8f6f4 v[0:3], v[4:11], v[4:11], v[0:3] @@ -18,6 +18,8 @@ v_mfma_f32_32x32x16_bf16 a[0:15], a[0:3], a[0:3], a[0:15] blgp:2 v_mfma_i32_16x16x64_i8 a[0:3], a[0:3], a[0:3], a[0:3] blgp:1 v_mfma_i32_16x16x64_i8 a[0:3], v[0:3], v[0:3], a[4:7] +v_mfma_i32_32x32x32_i8 v[0:15], v[0:3], v[0:3], v[0:15] +v_mfma_i32_32x32x32_i8 a[0:15], a[0:3], a[0:3], a[0:15] blgp:2 # CHECK: [0] [1] [2] [3] [4] [5] [6] Instructions: @@ -32,3 +34,5 @@ v_mfma_i32_16x16x64_i8 a[0:3], v[0:3], v[0:3], a[4:7] # CHECK-NEXT: - - - - - - 8.00 v_mfma_f32_32x32x16_bf16 a[0:15], a[0:3], a[0:3], a[0:15] blgp:2 # CHECK-NEXT: - - - - 1.00 - - v_mfma_i32_16x16x64_i8 a[0:3], a[0:3], a[0:3], a[0:3] blgp:1 # CHECK-NEXT: - - - - 1.00 - - v_mfma_i32_16x16x64_i8 a[0:3], v[0:3], v[0:3], a[4:7] +# CHECK-NEXT: - - - - 1.00 - - v_mfma_i32_32x32x32_i8 v[0:15], v[0:3], v[0:3], v[0:15] +# CHECK-NEXT: - - - - 1.00 - - v_mfma_i32_32x32x32_i8 a[0:15], a[0:3], a[0:3], a[0:15] blgp:2 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
