Author: Petr Penzin Date: 2024-11-19T14:20:55-08:00 New Revision: 41c86ca714a68eea8c73cf57fba28718d466660b
URL: https://github.com/llvm/llvm-project/commit/41c86ca714a68eea8c73cf57fba28718d466660b DIFF: https://github.com/llvm/llvm-project/commit/41c86ca714a68eea8c73cf57fba28718d466660b.diff LOG: [RISCV] Add TT-Ascalon-d8 processor (#115100) Ascalon is an out-of-order CPU core from Tenstorrent. Overview: https://tenstorrent.com/ip/tt-ascalon Adding 8-wide version, -mcpu=tt-ascalon-d8. Scheduling model will be added in a separate PR. --------- Co-authored-by: Anton Blanchard <ant...@tenstorrent.com> Added: Modified: clang/test/Driver/riscv-cpus.c clang/test/Misc/target-invalid-cpu-note/riscv.c llvm/docs/ReleaseNotes.md llvm/lib/Target/RISCV/RISCVProcessors.td Removed: ################################################################################ diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index d36639d16ad4cb..249216612f7ee7 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -104,6 +104,68 @@ // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-max | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-MAX %s // MTUNE-SYNTACORE-SCR1-MAX: "-tune-cpu" "syntacore-scr1-max" +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=tt-ascalon-d8 | FileCheck -check-prefix=MTUNE-TT-ASCALON-D8 %s +// MTUNE-TT-ASCALON-D8: "-tune-cpu" "tt-ascalon-d8" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=tt-ascalon-d8 | FileCheck -check-prefix=MCPU-TT-ASCALON-D8 %s +// MCPU-TT-ASCALON-D8: "-target-cpu" "tt-ascalon-d8" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+m" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+a" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+f" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+d" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+c" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+v" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+h" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicbom" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicbop" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicboz" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicntr" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicond" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicsr" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zifencei" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihintntl" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihintpause" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihpm" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zimop" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zmmul" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zawrs" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfa" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfbfmin" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfh" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfhmin" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zca" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zcb" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zba" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zbb" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zbs" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zkt" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvbb" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvbc" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve32f" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve32x" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64d" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64f" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64x" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfbfmin" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfbfwma" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfh" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfhmin" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkb" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkg" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkn" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvknc" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkned" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkng" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvknhb" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkt" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl128b" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl256b" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl32b" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl64b" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svinval" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svnapot" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svpbmt" + // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=veyron-v1 | FileCheck -check-prefix=MCPU-VEYRON-V1 %s // MCPU-VEYRON-V1: "-target-cpu" "veyron-v1" // MCPU-VEYRON-V1: "-target-feature" "+m" diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c index 7bbf3574af3c35..8c5df5884cd791 100644 --- a/clang/test/Misc/target-invalid-cpu-note/riscv.c +++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c @@ -41,6 +41,7 @@ // RISCV64-SAME: {{^}}, syntacore-scr4-rv64 // RISCV64-SAME: {{^}}, syntacore-scr5-rv64 // RISCV64-SAME: {{^}}, syntacore-scr7 +// RISCV64-SAME: {{^}}, tt-ascalon-d8 // RISCV64-SAME: {{^}}, veyron-v1 // RISCV64-SAME: {{^}}, xiangshan-nanhu // RISCV64-SAME: {{$}} @@ -87,6 +88,7 @@ // TUNE-RISCV64-SAME: {{^}}, syntacore-scr4-rv64 // TUNE-RISCV64-SAME: {{^}}, syntacore-scr5-rv64 // TUNE-RISCV64-SAME: {{^}}, syntacore-scr7 +// TUNE-RISCV64-SAME: {{^}}, tt-ascalon-d8 // TUNE-RISCV64-SAME: {{^}}, veyron-v1 // TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu // TUNE-RISCV64-SAME: {{^}}, generic diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 142db867b566ec..1ba3672baeed88 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -190,6 +190,7 @@ Changes to the RISC-V Backend * The `Zvbc32e` and `Zvkgs` extensions are now supported experimentally. * Added `Smctr`, `Ssctr` and `Svvptc` extensions. * `-mcpu=syntacore-scr7` was added. +* `-mcpu=tt-ascalon-d8` was added. * The `Zacas` extension is no longer marked as experimental. * Added Smdbltrp, Ssdbltrp extensions to -march. * The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index e52a856183678a..e96281bb46950e 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -407,6 +407,28 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", FeatureStdExtZkn], [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; +def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8", + NoSchedModel, + !listconcat(RVA23S64Features, + [FeatureStdExtSmaia, + FeatureStdExtSsaia, + FeatureStdExtSscofpmf, + FeatureStdExtSsstrict, + FeatureStdExtZfbfmin, + FeatureStdExtZfh, + FeatureStdExtZicsr, + FeatureStdExtZvbc, + FeatureStdExtZvfbfmin, + FeatureStdExtZvfbfwma, + FeatureStdExtZvfh, + FeatureStdExtZvkng, + FeatureStdExtZvl256b, + FeatureUnalignedScalarMem, + FeatureUnalignedVectorMem]), + [TuneNoDefaultUnroll, + TuneOptimizedZeroStrideLoad, + FeaturePostRAScheduler]>; + def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1", NoSchedModel, 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