Author: dong-miao Date: 2024-10-28T22:54:51+11:00 New Revision: 75c75fc16e8a202668cfa71404724117b22336b9
URL: https://github.com/llvm/llvm-project/commit/75c75fc16e8a202668cfa71404724117b22336b9 DIFF: https://github.com/llvm/llvm-project/commit/75c75fc16e8a202668cfa71404724117b22336b9.diff LOG: [RISCV]Add svvptc extension (#113882) Added: Modified: clang/test/Driver/print-supported-extensions-riscv.c clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.md llvm/lib/Target/RISCV/RISCVFeatures.td llvm/test/CodeGen/RISCV/attributes.ll llvm/test/MC/RISCV/attribute-arch.s llvm/unittests/TargetParser/RISCVISAInfoTest.cpp Removed: ################################################################################ diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index fc8a9c04667b6b..4d93144724dffb 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -147,6 +147,7 @@ // CHECK-NEXT: svinval 1.0 'Svinval' (Fine-Grained Address-Translation Cache Invalidation) // CHECK-NEXT: svnapot 1.0 'Svnapot' (NAPOT Translation Contiguity) // CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory Types) +// CHECK-NEXT: svvptc 1.0 'svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid) // CHECK-NEXT: xcvalu 1.0 'XCValu' (CORE-V ALU Operations) // CHECK-NEXT: xcvbi 1.0 'XCVbi' (CORE-V Immediate Branching) // CHECK-NEXT: xcvbitmanip 1.0 'XCVbitmanip' (CORE-V Bit Manipulation) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 6e586714af84d3..597325ffa5e4ee 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -52,6 +52,7 @@ // CHECK-NOT: __riscv_svinval {{.*$}} // CHECK-NOT: __riscv_svnapot {{.*$}} // CHECK-NOT: __riscv_svpbmt {{.*$}} +// CHECK-NOT: __riscv_svvptc {{.*$}} // CHECK-NOT: __riscv_v {{.*$}} // CHECK-NOT: __riscv_v_elen {{.*$}} // CHECK-NOT: __riscv_v_elen_fp {{.*$}} @@ -516,6 +517,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SVPBMT-EXT %s // CHECK-SVPBMT-EXT: __riscv_svpbmt 1000000{{$}} +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32isvvptc -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SVVPTC-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64isvvptc -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SVVPTC-EXT %s +// CHECK-SVVPTC-EXT: __riscv_svvptc 1000000{{$}} + // RUN: %clang --target=riscv32-unknown-linux-gnu \ // RUN: -march=rv32iv1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 6075a2289d473d..dae6f7c46cc48c 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -156,6 +156,7 @@ on support follow. ``Svinval`` Assembly Support ``Svnapot`` Assembly Support ``Svpbmt`` Supported + ``Svvptc`` Supported ``V`` Supported ``Za128rs`` Supported (`See note <#riscv-profiles-extensions-note>`__) ``Za64rs`` Supported (`See note <#riscv-profiles-extensions-note>`__) diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index f7215279940d69..22a32d110855d5 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -178,7 +178,7 @@ Changes to the RISC-V Backend means Zve32x and Zve32f will also require Zvl64b. The prior support was largely untested. * The `Zvbc32e` and `Zvkgs` extensions are now supported experimentally. -* Added `Smctr` and `Ssctr` extensions. +* Added `Smctr`, `Ssctr` and `Svvptc` extensions. * `-mcpu=syntacore-scr7` was added. * The `Zacas` extension is no longer marked as experimental. * The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 559f0e5950eddd..608782d7839a9f 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1029,6 +1029,10 @@ def FeatureStdExtSvpbmt : RISCVExtension<"svpbmt", 1, 0, "'Svpbmt' (Page-Based Memory Types)">; +def FeatureStdExtSvvptc + : RISCVExtension<"svvptc", 1, 0, + "'svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)">; + def FeatureStdExtSha : RISCVExtension<"sha", 1, 0, "'Sha' (Augmented Hypervisor)", diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 5c835befd6f505..e5b308a172661c 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -62,6 +62,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+svbare %s -o - | FileCheck --check-prefixes=CHECK,RV32SVBARE %s ; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV32SVNAPOT %s ; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SVPBMT %s +; RUN: llc -mtriple=riscv32 -mattr=+svvptc %s -o - | FileCheck --check-prefixes=CHECK,RV32SVVPTC %s ; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV32SVINVAL %s ; RUN: llc -mtriple=riscv32 -mattr=+xcvalu %s -o - | FileCheck --check-prefix=RV32XCVALU %s ; RUN: llc -mtriple=riscv32 -mattr=+xcvbitmanip %s -o - | FileCheck --check-prefix=RV32XCVBITMANIP %s @@ -202,6 +203,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+svbare %s -o - | FileCheck --check-prefixes=CHECK,RV64SVBARE %s ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV64SVNAPOT %s ; RUN: llc -mtriple=riscv64 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV64SVPBMT %s +; RUN: llc -mtriple=riscv64 -mattr=+svvptc %s -o - | FileCheck --check-prefixes=CHECK,RV64SVVPTC %s ; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV64SVINVAL %s ; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefixes=CHECK,RV64XVENTANACONDOPS %s ; RUN: llc -mtriple=riscv64 -mattr=+xsfvfwmaccqqq %s -o - | FileCheck --check-prefix=RV64XSFVFWMACCQQQ %s @@ -358,6 +360,7 @@ ; RV32SVBARE: .attribute 5, "rv32i2p1_svbare1p0" ; RV32SVNAPOT: .attribute 5, "rv32i2p1_svnapot1p0" ; RV32SVPBMT: .attribute 5, "rv32i2p1_svpbmt1p0" +; RV32SVVPTC: .attribute 5, "rv32i2p1_svvptc1p0" ; RV32SVINVAL: .attribute 5, "rv32i2p1_svinval1p0" ; RV32XCVALU: .attribute 5, "rv32i2p1_xcvalu1p0" ; RV32XCVBITMANIP: .attribute 5, "rv32i2p1_xcvbitmanip1p0" @@ -500,6 +503,7 @@ ; RV64SVBARE: .attribute 5, "rv64i2p1_svbare1p0" ; RV64SVNAPOT: .attribute 5, "rv64i2p1_svnapot1p0" ; RV64SVPBMT: .attribute 5, "rv64i2p1_svpbmt1p0" +; RV64SVVPTC: .attribute 5, "rv64i2p1_svvptc1p0" ; RV64SVINVAL: .attribute 5, "rv64i2p1_svinval1p0" ; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p1_xventanacondops1p0" ; RV64XSFVFWMACCQQQ: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0_xsfvfwmaccqqq1p0" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 2332bcacc99d06..a744a660a7076f 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -375,6 +375,9 @@ .attribute arch, "rv32i_svbare1p0" # CHECK: attribute 5, "rv32i2p1_svbare1p0" +.attribute arch, "rv32i_svvptc1p0" +# CHECK: attribute 5, "rv32i2p1_svvptc1p0" + .attribute arch, "rv32i_zfbfmin1p0" # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0" diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index e402b1a40de34d..30b5f3ce3cb084 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1092,6 +1092,7 @@ R"(All available -march extensions for RISC-V svinval 1.0 svnapot 1.0 svpbmt 1.0 + svvptc 1.0 xcvalu 1.0 xcvbi 1.0 xcvbitmanip 1.0 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
