llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang @llvm/pr-subscribers-backend-aarch64 Author: Jonathan Thackray (jthackray) <details> <summary>Changes</summary> Add support for the following Armv9.6-A architecture extensions: * FEAT_PoPS - Point of Physical Storage as documented here: https://developer.arm.com/documentation/109697/2024_09/Feature-descriptions/The-Armv9-6-architecture-extension --- Full diff: https://github.com/llvm/llvm-project/pull/113496.diff 8 Files Affected: - (modified) clang/test/Driver/aarch64-v96a.c (+4) - (modified) clang/test/Driver/print-supported-extensions-aarch64.c (+1) - (modified) llvm/lib/Target/AArch64/AArch64Features.td (+3) - (modified) llvm/lib/Target/AArch64/AArch64SystemOperands.td (+7) - (modified) llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (+1) - (added) llvm/test/MC/AArch64/armv9.6a-ras.s (+12) - (added) llvm/test/MC/Disassembler/AArch64/armv9.6a-ras.txt (+11) - (modified) llvm/unittests/TargetParser/TargetParserTest.cpp (+3-1) ``````````diff diff --git a/clang/test/Driver/aarch64-v96a.c b/clang/test/Driver/aarch64-v96a.c index 343e347c928cabc..de7890140ebd3a0 100644 --- a/clang/test/Driver/aarch64-v96a.c +++ b/clang/test/Driver/aarch64-v96a.c @@ -65,4 +65,8 @@ // RUN: %clang -target aarch64 -march=armv9.6a+pcdphint -### -c %s 2>&1 | FileCheck -check-prefix=V96A-PCDPHINT %s // RUN: %clang -target aarch64 -march=armv9.6-a+pcdphint -### -c %s 2>&1 | FileCheck -check-prefix=V96A-PCDPHINT %s // V96A-PCDPHINT: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.6a"{{.*}} "-target-feature" "+pcdphint" + +// RUN: %clang -target aarch64 -march=armv9.6a+pops -### -c %s 2>&1 | FileCheck -check-prefix=V96A-POPS %s +// RUN: %clang -target aarch64 -march=armv9.6-a+pops -### -c %s 2>&1 | FileCheck -check-prefix=V96A-POPS %s +// V96A-POPS: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.6a"{{.*}} "-target-feature" "+pops" // diff --git a/clang/test/Driver/print-supported-extensions-aarch64.c b/clang/test/Driver/print-supported-extensions-aarch64.c index 7ff4f17beff75ed..03eacf99736f9e1 100644 --- a/clang/test/Driver/print-supported-extensions-aarch64.c +++ b/clang/test/Driver/print-supported-extensions-aarch64.c @@ -50,6 +50,7 @@ // CHECK-NEXT: pauth-lr FEAT_PAuth_LR Enable Armv9.5-A PAC enhancements // CHECK-NEXT: pcdphint FEAT_PCDPHINT Enable Armv9.6-A Producer Consumer Data Placement hints // CHECK-NEXT: pmuv3 FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension +// CHECK-NEXT: pops FEAT_PoPS Enable Armv9.6-A Point Of Physical Storage (PoPS) DC instructions // CHECK-NEXT: predres FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions // CHECK-NEXT: rng FEAT_RNG Enable Random Number generation instructions // CHECK-NEXT: ras FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td index 476d5a4e093efa8..5dd8a93103a3237 100644 --- a/llvm/lib/Target/AArch64/AArch64Features.td +++ b/llvm/lib/Target/AArch64/AArch64Features.td @@ -564,6 +564,9 @@ def FeatureOCCMO: ExtensionWithMArch<"occmo", "OCCMO", "FEAT_OCCMO", def FeaturePCDPHINT: ExtensionWithMArch<"pcdphint", "PCDPHINT", "FEAT_PCDPHINT", "Enable Armv9.6-A Producer Consumer Data Placement hints">; +def FeaturePoPS: ExtensionWithMArch<"pops", "PoPS", "FEAT_PoPS", + "Enable Armv9.6-A Point Of Physical Storage (PoPS) DC instructions">; + //===----------------------------------------------------------------------===// // Other Features //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td index 1d2bb1d732346cd..f26bed62c59c6e6 100644 --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -2048,3 +2048,10 @@ let Requires = [{ {AArch64::FeaturePCDPHINT} }] in { // v9.6a Realm management extension enhancements def : RWSysReg<"GPCBW_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b101>; + +// v9.6 FEAT_PoPS +// +let Requires = [{ {AArch64::FeaturePoPS} }] in { +def : DC<"CIGDVAPS", 0b000, 0b0111, 0b1111, 0b101>; +def : DC<"CIVAPS", 0b000, 0b0111, 0b1111, 0b001>; +} diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 3ab4ebbf6ebf074..dfc5e04110cf57b 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -3794,6 +3794,7 @@ static const struct Extension { {"sme-fa64", {AArch64::FeatureSMEFA64}}, {"cpa", {AArch64::FeatureCPA}}, {"tlbiw", {AArch64::FeatureTLBIW}}, + {"pops", {AArch64::FeaturePoPS}}, {"cmpbr", {AArch64::FeatureCMPBR}}, {"f8f32mm", {AArch64::FeatureF8F32MM}}, {"f8f16mm", {AArch64::FeatureF8F16MM}}, diff --git a/llvm/test/MC/AArch64/armv9.6a-ras.s b/llvm/test/MC/AArch64/armv9.6a-ras.s new file mode 100644 index 000000000000000..2a188d7613d5692 --- /dev/null +++ b/llvm/test/MC/AArch64/armv9.6a-ras.s @@ -0,0 +1,12 @@ +// RUN: not llvm-mc -triple aarch64 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix NO-POPS +// RUN: llvm-mc -triple aarch64 -mattr=+pops -show-encoding < %s 2>&1 | FileCheck %s --check-prefix HAS-POPS + +dc CIGDVAPS, x3 +dc CIVAPS, x3 +// NO-POPS: error: DC CIGDVAPS requires: pops +// NO-POPS: error: DC CIVAPS requires: pops + +# HAS-POPS: .text + +# HAS-POPS: dc cigdvaps, x3 // encoding: [0xa3,0x7f,0x08,0xd5] +# HAS-POPS-NEXT: dc civaps, x3 // encoding: [0x23,0x7f,0x08,0xd5] diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.6a-ras.txt b/llvm/test/MC/Disassembler/AArch64/armv9.6a-ras.txt new file mode 100644 index 000000000000000..d6bf65765d3b604 --- /dev/null +++ b/llvm/test/MC/Disassembler/AArch64/armv9.6a-ras.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple aarch64 -mattr=+pops -disassemble < %s | FileCheck %s + +#------------------------------------------------------------------------------ +# ARMV9.6-A RAS Extensions +#------------------------------------------------------------------------------ + +[0xa3,0x7f,0x08,0xd5] +# CHECK: dc cigdvaps, x3 + +[0x23,0x7f,0x08,0xd5] +# CHECK: dc civaps, x3 diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 572006166d0d8bd..4e856de4ea9c479 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1333,7 +1333,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) { AArch64::AEK_F8F16MM, AArch64::AEK_LSFE, AArch64::AEK_FPRCVT, AArch64::AEK_CMPBR, AArch64::AEK_LSUI, AArch64::AEK_OCCMO, - AArch64::AEK_PCDPHINT, + AArch64::AEK_PCDPHINT, AArch64::AEK_POPS, }; std::vector<StringRef> Features; @@ -1437,6 +1437,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) { EXPECT_TRUE(llvm::is_contained(Features, "+lsui")); EXPECT_TRUE(llvm::is_contained(Features, "+occmo")); EXPECT_TRUE(llvm::is_contained(Features, "+pcdphint")); + EXPECT_TRUE(llvm::is_contained(Features, "+pops")); // Assuming we listed every extension above, this should produce the same // result. @@ -1592,6 +1593,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) { {"lsui", "nolsui", "+lsui", "-lsui"}, {"occmo", "nooccmo", "+occmo", "-occmo"}, {"pcdphint", "nopcdphint", "+pcdphint", "-pcdphint"}, + {"pops", "nopops", "+pops", "-pops"}, }; for (unsigned i = 0; i < std::size(ArchExt); i++) { `````````` </details> https://github.com/llvm/llvm-project/pull/113496 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
