================
@@ -348,6 +349,14 @@ bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr
*MI, unsigned OpNo,
if (!MO.isReg())
OS << 'i';
return false;
+ case 'N': // Print the register encoding as an integer (0-31, or 0-7 when
----------------
lenary wrote:
Ah, yes, sorry - this comment wasn't updated when the implementation was, I'll
fix the comment.
I specifically gave up on just printing the RVC encoding when the constraint is
`c*`, because that makes it harder to use the register in both RVC and non-RVC
positions in a multi-instruction inline assembly statement. Instead, it's up to
the assembly author to correctly mask the value from the full encoding down to
the RVC encoding.
https://github.com/llvm/llvm-project/pull/112561
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