alex-t wrote: > > Although, revisiting this now, I still don't understand why they decided to > > include ALL spill opcodes in the prologue, but not only the SGPR spills? > > Clearly, none of the VGPR reloads really belong to the prologue. > > At a first glance, changing the isSpill(opcode) to isSGPRSpill(opcode) in > > the snippet below would solve the initial case. ` return > > IsNullOrVectorRegister && (isSpill(Opcode) || (!MI.isTerminator() && Opcode > > != AMDGPU::COPY && MI.modifiesRegister(AMDGPU::EXEC, &RI))); }` > > I need to look at this a bit more. I am sure they would have done this if > > such a simple change had solved the problem. > > I like this change - it fixes the problem I reported in #109294.
It fixes the problem but requires us to consider WWM reloads as prologue instructions. Any VGPR reload starts a new live range and possibly introduces interference. CD's reply here (https://github.com/llvm/llvm-project/pull/111496#issuecomment-2411434387) made me hope that it would work. However, I would like to see the corresponding MIR test as proof. https://github.com/llvm/llvm-project/pull/108596 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
