andrewcarlotti wrote: > However the architecture does not mandate that both need to be implemented at > the same time.
This premise is incorrect. For FEAT_SVE_AES and FEAT_SVE_PMULL128, the latest version of the Arm ARM (DDI 0487K.a) includes the following in the definition of `ID_AA64ZFR0_EL1.AES`: > FEAT_SVE_AES implements the functionality identified by the value 0b0001. FEAT_SVE_PMULL128 implements the functionality identified by the value 0b0010. The permitted values are 0b0000 and 0b0010. So it isn't permitted to implement just one of FEAT_SVE_AES and FEAT_SVE_PMULL128. Similarly, for FEAT_AES and FEAT_PMULL, the previous version of the Arm ARM (DDI 0487J.a) includes the following in the definition of `ID_AA64ISAR0_EL1.AES`: >FEAT_AES implements the functionality identified by the value 0b0001. FEAT_PMULL implements the functionality identified by the value 0b0010. >From Armv8, the permitted values are 0b0000 and 0b0010. This last line was deleted in the latest Arm ARM (DDI 0487K.a), but it appears to be a mistake that was not intended to relax the architecture constraints. I've reported this discrepancy internally. https://github.com/llvm/llvm-project/pull/110816 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
