llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang-codegen Author: Lei Huang (lei137) <details> <summary>Changes</summary> Fixes #<!-- -->107229 --- Full diff: https://github.com/llvm/llvm-project/pull/108606.diff 3 Files Affected: - (modified) clang/lib/CodeGen/CGBuiltin.cpp (+1-1) - (modified) clang/test/CodeGen/PowerPC/builtins-ppc-build-pair-mma.c (+1-1) - (modified) clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c (+4-4) ``````````diff diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index a52e880a764252..5db5ad5470c366 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -18197,7 +18197,7 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID, CallOps.push_back(Ops[i]); llvm::Function *F = CGM.getIntrinsic(ID); Value *Call = Builder.CreateCall(F, CallOps); - return Builder.CreateAlignedStore(Call, Ops[0], MaybeAlign(64)); + return Builder.CreateAlignedStore(Call, Ops[0], MaybeAlign()); } case PPC::BI__builtin_ppc_compare_and_swap: diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-build-pair-mma.c b/clang/test/CodeGen/PowerPC/builtins-ppc-build-pair-mma.c index 8a2bc93dd6cd0a..cdbfdd6b7975ad 100644 --- a/clang/test/CodeGen/PowerPC/builtins-ppc-build-pair-mma.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-build-pair-mma.c @@ -99,7 +99,7 @@ void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc1, vec // CHECK-LE-NOOPT-NEXT: [[TMP4:%.*]] = load <16 x i8>, ptr [[VC1_ADDR]], align 16 // CHECK-LE-NOOPT-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[VC2_ADDR]], align 16 // CHECK-LE-NOOPT-NEXT: [[TMP6:%.*]] = call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[TMP5]], <16 x i8> [[TMP4]]) -// CHECK-LE-NOOPT-NEXT: store <256 x i1> [[TMP6]], ptr [[RES]], align 64 +// CHECK-LE-NOOPT-NEXT: store <256 x i1> [[TMP6]], ptr [[RES]], align 32 // CHECK-LE-NOOPT-NEXT: [[TMP7:%.*]] = load <256 x i1>, ptr [[RES]], align 32 // CHECK-LE-NOOPT-NEXT: [[TMP8:%.*]] = load ptr, ptr [[RESP_ADDR]], align 8 // CHECK-LE-NOOPT-NEXT: store <256 x i1> [[TMP7]], ptr [[TMP8]], align 32 diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c b/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c index 39c040967dc0c3..b18bb3ad050aca 100644 --- a/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c @@ -85,11 +85,11 @@ void testVQLocal(int *ptr, vector unsigned char vc) { // CHECK-NEXT: [[TMP3:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16 // CHECK-NEXT: [[TMP4:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16 // CHECK-NEXT: [[TMP5:%.*]] = call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[TMP3]], <16 x i8> [[TMP4]]) -// CHECK-NEXT: store <256 x i1> [[TMP5]], ptr [[VP2]], align 64 +// CHECK-NEXT: store <256 x i1> [[TMP5]], ptr [[VP2]], align 32 // CHECK-NEXT: [[TMP6:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16 // CHECK-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16 // CHECK-NEXT: [[TMP8:%.*]] = call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[TMP7]], <16 x i8> [[TMP6]]) -// CHECK-NEXT: store <256 x i1> [[TMP8]], ptr [[VP2]], align 64 +// CHECK-NEXT: store <256 x i1> [[TMP8]], ptr [[VP2]], align 32 // CHECK-NEXT: [[TMP9:%.*]] = load <256 x i1>, ptr [[VP3]], align 32 // CHECK-NEXT: [[TMP10:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16 // CHECK-NEXT: [[TMP11:%.*]] = call <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1> [[TMP9]], <16 x i8> [[TMP10]]) @@ -118,11 +118,11 @@ void testVQLocal(int *ptr, vector unsigned char vc) { // CHECK-BE-NEXT: [[TMP3:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16 // CHECK-BE-NEXT: [[TMP4:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16 // CHECK-BE-NEXT: [[TMP5:%.*]] = call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[TMP3]], <16 x i8> [[TMP4]]) -// CHECK-BE-NEXT: store <256 x i1> [[TMP5]], ptr [[VP2]], align 64 +// CHECK-BE-NEXT: store <256 x i1> [[TMP5]], ptr [[VP2]], align 32 // CHECK-BE-NEXT: [[TMP6:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16 // CHECK-BE-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16 // CHECK-BE-NEXT: [[TMP8:%.*]] = call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[TMP6]], <16 x i8> [[TMP7]]) -// CHECK-BE-NEXT: store <256 x i1> [[TMP8]], ptr [[VP2]], align 64 +// CHECK-BE-NEXT: store <256 x i1> [[TMP8]], ptr [[VP2]], align 32 // CHECK-BE-NEXT: [[TMP9:%.*]] = load <256 x i1>, ptr [[VP3]], align 32 // CHECK-BE-NEXT: [[TMP10:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16 // CHECK-BE-NEXT: [[TMP11:%.*]] = call <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1> [[TMP9]], <16 x i8> [[TMP10]]) `````````` </details> https://github.com/llvm/llvm-project/pull/108606 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
