================
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb<string OpcodeStr,
AVX512VLVectorVTInfo _dest,
defm VCVTHF82PH : avx10_convert_2op_nomb<"vcvthf82ph", avx512vl_f16_info,
avx512vl_i8_info, 0x1e,
X86vcvthf82ph>,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-------------------------------------------------
+// AVX10 BF16 instructions
+//-------------------------------------------------
+
+// VADDNEPBF16, VSUBNEPBF16, VMULNEPBF16, VDIVNEPBF16, VMAXPBF16, VMINPBF16
+multiclass avx10_fp_binopne_int_pbf16<bits<8> opc, string OpcodeStr,
+ X86SchedWriteSizes sched,
+ bit IsCommutable = 0> {
+ let Predicates = [HasAVX10_2_512] in
+ defm PBF16Z : avx512_fp_packed<opc, OpcodeStr,
+
!cast<Intrinsic>("int_x86_avx10_"#OpcodeStr#"pbf16512"),
+
!cast<Intrinsic>("int_x86_avx10_"#OpcodeStr#"pbf16512"),
+ v32bf16_info, sched.PH.ZMM, IsCommutable>,
EVEX_V512,
+ T_MAP5, PD, EVEX_CD8<16, CD8VF>;
+ let Predicates = [HasAVX10_2] in {
+ defm PBF16Z128 : avx512_fp_packed<opc, OpcodeStr,
+
!cast<Intrinsic>("int_x86_avx10_"#OpcodeStr#"pbf16128"),
+
!cast<Intrinsic>("int_x86_avx10_"#OpcodeStr#"pbf16128"),
+ v8bf16x_info, sched.PH.XMM, IsCommutable>,
EVEX_V128,
+ T_MAP5, PD, EVEX_CD8<16, CD8VF>;
+ defm PBF16Z256 : avx512_fp_packed<opc, OpcodeStr,
+
!cast<Intrinsic>("int_x86_avx10_"#OpcodeStr#"pbf16256"),
+
!cast<Intrinsic>("int_x86_avx10_"#OpcodeStr#"pbf16256"),
+ v16bf16x_info, sched.PH.YMM, IsCommutable>,
EVEX_V256,
+ T_MAP5, PD, EVEX_CD8<16, CD8VF>;
+ }
+}
+
+multiclass avx10_fp_binop_pbf16<bits<8> opc, string OpcodeStr,
SDPatternOperator OpNode,
+ X86SchedWriteSizes sched,
+ bit IsCommutable = 0,
+ SDPatternOperator MaskOpNode = OpNode> {
+ let Predicates = [HasAVX10_2_512] in
+ defm NEPBF16Z : avx512_fp_packed<opc, OpcodeStr, OpNode, MaskOpNode,
+ v32bf16_info, sched.PH.ZMM, IsCommutable>,
EVEX_V512,
+ T_MAP5, PD, EVEX_CD8<16, CD8VF>;
+ let Predicates = [HasAVX10_2] in {
+ defm NEPBF16Z128 : avx512_fp_packed<opc, OpcodeStr, OpNode, MaskOpNode,
+ v8bf16x_info, sched.PH.XMM, IsCommutable>,
EVEX_V128,
+ T_MAP5, PD, EVEX_CD8<16, CD8VF>;
+ defm NEPBF16Z256 : avx512_fp_packed<opc, OpcodeStr, OpNode, MaskOpNode,
+ v16bf16x_info, sched.PH.YMM, IsCommutable>,
EVEX_V256,
+ T_MAP5, PD, EVEX_CD8<16, CD8VF>;
+ }
+}
+
+let Uses = []<Register>, mayRaiseFPException = 0 in {
+defm VADD : avx10_fp_binop_pbf16<0x58, "vaddne", fadd, SchedWriteFAddSizes, 1>;
+defm VSUB : avx10_fp_binop_pbf16<0x5C, "vsubne", fsub, SchedWriteFAddSizes, 0>;
+defm VMUL : avx10_fp_binop_pbf16<0x59, "vmulne", fmul, SchedWriteFMulSizes, 0>;
----------------
FreddyLeaf wrote:
[7957436](https://github.com/llvm/llvm-project/pull/101603/commits/7957436ac07d1902f3f510de756577c00353dd02)
https://github.com/llvm/llvm-project/pull/101603
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