https://github.com/v01dXYZ created https://github.com/llvm/llvm-project/pull/105766
Fixes https://github.com/llvm/llvm-project/issues/104614 >From 9861e901f45671f9bcf9398884dea54275d99520 Mon Sep 17 00:00:00 2001 From: v01dxyz <v01d...@v01d.xyz> Date: Wed, 21 Aug 2024 23:03:01 +0200 Subject: [PATCH] (Draft) [Clang][AArch64] Diagnose invalid system register name --- clang/include/clang/Basic/TargetInfo.h | 4 + clang/include/clang/Sema/SemaARM.h | 3 +- clang/lib/Basic/TargetInfo.cpp | 16 + clang/lib/Basic/Targets/AArch64.cpp | 1219 ++++++++++++++++++++ clang/lib/Basic/Targets/AArch64.h | 3 + clang/lib/Sema/SemaARM.cpp | 52 +- clang/test/Sema/aarch64-special-register.c | 23 +- 7 files changed, 1291 insertions(+), 29 deletions(-) diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h index a58fb5f9792720..95de44a1554900 100644 --- a/clang/include/clang/Basic/TargetInfo.h +++ b/clang/include/clang/Basic/TargetInfo.h @@ -1062,6 +1062,7 @@ class TargetInfo : public TransferrableTargetInfo, /// /// This is used by Sema for inline asm statements. virtual bool isValidGCCRegisterName(StringRef Name) const; + virtual bool isValidSystemRegisterName(StringRef Name) const; /// Returns the "normalized" GCC register name. /// @@ -1850,6 +1851,9 @@ class TargetInfo : public TransferrableTargetInfo, return PtrDiffType; } virtual ArrayRef<const char *> getGCCRegNames() const = 0; + virtual ArrayRef<const char *> getSystemRegNames() const { + return std::nullopt; + } virtual ArrayRef<GCCRegAlias> getGCCRegAliases() const = 0; virtual ArrayRef<AddlRegName> getGCCAddlRegNames() const { return std::nullopt; diff --git a/clang/include/clang/Sema/SemaARM.h b/clang/include/clang/Sema/SemaARM.h index fedc7df7908f17..03aa9882724d8c 100644 --- a/clang/include/clang/Sema/SemaARM.h +++ b/clang/include/clang/Sema/SemaARM.h @@ -56,7 +56,8 @@ class SemaARM : public SemaBase { bool CheckAArch64BuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, CallExpr *TheCall); - bool BuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall, int ArgNum, + bool BuiltinARMSpecialReg(const TargetInfo &TI, unsigned BuiltinID, + CallExpr *TheCall, int ArgNum, unsigned ExpectedFieldNum, bool AllowName); bool BuiltinARMMemoryTaggingCall(unsigned BuiltinID, CallExpr *TheCall); diff --git a/clang/lib/Basic/TargetInfo.cpp b/clang/lib/Basic/TargetInfo.cpp index 29f5cd14e46e11..6f9878355989d1 100644 --- a/clang/lib/Basic/TargetInfo.cpp +++ b/clang/lib/Basic/TargetInfo.cpp @@ -681,6 +681,22 @@ bool TargetInfo::isValidGCCRegisterName(StringRef Name) const { return false; } +bool TargetInfo::isValidSystemRegisterName(StringRef Name) const { + if (Name.empty()) + return false; + + ArrayRef<const char *> Names = getSystemRegNames(); + + if (Names.empty()) + return true; + + // Check register names. + if (llvm::is_contained(Names, Name.upper())) + return true; + + return false; +} + StringRef TargetInfo::getNormalizedGCCRegisterName(StringRef Name, bool ReturnCanonical) const { assert(isValidGCCRegisterName(Name) && "Invalid register passed in"); diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp index 6ba31cc05a0d75..cc6e523b3da94d 100644 --- a/clang/lib/Basic/Targets/AArch64.cpp +++ b/clang/lib/Basic/Targets/AArch64.cpp @@ -1232,6 +1232,1221 @@ TargetInfo::BuiltinVaListKind AArch64TargetInfo::getBuiltinVaListKind() const { return TargetInfo::AArch64ABIBuiltinVaList; } +const char *const AArch64TargetInfo::SystemRegNames[] = { + "ACCDATA_EL1", + "ACTLR_EL1", + "ACTLR_EL2", + "ACTLR_EL3", + "AFSR0_EL1", + "AFSR0_EL12", + "AFSR0_EL2", + "AFSR0_EL3", + "AFSR1_EL1", + "AFSR1_EL12", + "AFSR1_EL2", + "AFSR1_EL3", + "AIDR_EL1", + "ALLINT", + "AMAIR2_EL1", + "AMAIR2_EL12", + "AMAIR2_EL2", + "AMAIR2_EL3", + "AMAIR_EL1", + "AMAIR_EL12", + "AMAIR_EL2", + "AMAIR_EL3", + "AMCFGR_EL0", + "AMCG1IDR_EL0", + "AMCGCR_EL0", + "AMCNTENCLR0_EL0", + "AMCNTENCLR1_EL0", + "AMCNTENSET0_EL0", + "AMCNTENSET1_EL0", + "AMCR_EL0", + "AMEVCNTR00_EL0", + "AMEVCNTR01_EL0", + "AMEVCNTR02_EL0", + "AMEVCNTR03_EL0", + "AMEVCNTR10_EL0", + "AMEVCNTR110_EL0", + "AMEVCNTR111_EL0", + "AMEVCNTR112_EL0", + "AMEVCNTR113_EL0", + "AMEVCNTR114_EL0", + "AMEVCNTR115_EL0", + "AMEVCNTR11_EL0", + "AMEVCNTR12_EL0", + "AMEVCNTR13_EL0", + "AMEVCNTR14_EL0", + "AMEVCNTR15_EL0", + "AMEVCNTR16_EL0", + "AMEVCNTR17_EL0", + "AMEVCNTR18_EL0", + "AMEVCNTR19_EL0", + "AMEVCNTVOFF00_EL2", + "AMEVCNTVOFF010_EL2", + "AMEVCNTVOFF011_EL2", + "AMEVCNTVOFF012_EL2", + "AMEVCNTVOFF013_EL2", + "AMEVCNTVOFF014_EL2", + "AMEVCNTVOFF015_EL2", + "AMEVCNTVOFF01_EL2", + "AMEVCNTVOFF02_EL2", + "AMEVCNTVOFF03_EL2", + "AMEVCNTVOFF04_EL2", + "AMEVCNTVOFF05_EL2", + "AMEVCNTVOFF06_EL2", + "AMEVCNTVOFF07_EL2", + "AMEVCNTVOFF08_EL2", + "AMEVCNTVOFF09_EL2", + "AMEVCNTVOFF10_EL2", + "AMEVCNTVOFF110_EL2", + "AMEVCNTVOFF111_EL2", + "AMEVCNTVOFF112_EL2", + "AMEVCNTVOFF113_EL2", + "AMEVCNTVOFF114_EL2", + "AMEVCNTVOFF115_EL2", + "AMEVCNTVOFF11_EL2", + "AMEVCNTVOFF12_EL2", + "AMEVCNTVOFF13_EL2", + "AMEVCNTVOFF14_EL2", + "AMEVCNTVOFF15_EL2", + "AMEVCNTVOFF16_EL2", + "AMEVCNTVOFF17_EL2", + "AMEVCNTVOFF18_EL2", + "AMEVCNTVOFF19_EL2", + "AMEVTYPER00_EL0", + "AMEVTYPER01_EL0", + "AMEVTYPER02_EL0", + "AMEVTYPER03_EL0", + "AMEVTYPER10_EL0", + "AMEVTYPER110_EL0", + "AMEVTYPER111_EL0", + "AMEVTYPER112_EL0", + "AMEVTYPER113_EL0", + "AMEVTYPER114_EL0", + "AMEVTYPER115_EL0", + "AMEVTYPER11_EL0", + "AMEVTYPER12_EL0", + "AMEVTYPER13_EL0", + "AMEVTYPER14_EL0", + "AMEVTYPER15_EL0", + "AMEVTYPER16_EL0", + "AMEVTYPER17_EL0", + "AMEVTYPER18_EL0", + "AMEVTYPER19_EL0", + "AMUSERENR_EL0", + "APDAKEYHI_EL1", + "APDAKEYLO_EL1", + "APDBKEYHI_EL1", + "APDBKEYLO_EL1", + "APGAKEYHI_EL1", + "APGAKEYLO_EL1", + "APIAKEYHI_EL1", + "APIAKEYLO_EL1", + "APIBKEYHI_EL1", + "APIBKEYLO_EL1", + "BRBCR_EL1", + "BRBCR_EL12", + "BRBCR_EL2", + "BRBFCR_EL1", + "BRBIDR0_EL1", + "BRBINF0_EL1", + "BRBINF10_EL1", + "BRBINF11_EL1", + "BRBINF12_EL1", + "BRBINF13_EL1", + "BRBINF14_EL1", + "BRBINF15_EL1", + "BRBINF16_EL1", + "BRBINF17_EL1", + "BRBINF18_EL1", + "BRBINF19_EL1", + "BRBINF1_EL1", + "BRBINF20_EL1", + "BRBINF21_EL1", + "BRBINF22_EL1", + "BRBINF23_EL1", + "BRBINF24_EL1", + "BRBINF25_EL1", + "BRBINF26_EL1", + "BRBINF27_EL1", + "BRBINF28_EL1", + "BRBINF29_EL1", + "BRBINF2_EL1", + "BRBINF30_EL1", + "BRBINF31_EL1", + "BRBINF3_EL1", + "BRBINF4_EL1", + "BRBINF5_EL1", + "BRBINF6_EL1", + "BRBINF7_EL1", + "BRBINF8_EL1", + "BRBINF9_EL1", + "BRBINFINJ_EL1", + "BRBSRC0_EL1", + "BRBSRC10_EL1", + "BRBSRC11_EL1", + "BRBSRC12_EL1", + "BRBSRC13_EL1", + "BRBSRC14_EL1", + "BRBSRC15_EL1", + "BRBSRC16_EL1", + "BRBSRC17_EL1", + "BRBSRC18_EL1", + "BRBSRC19_EL1", + "BRBSRC1_EL1", + "BRBSRC20_EL1", + "BRBSRC21_EL1", + "BRBSRC22_EL1", + "BRBSRC23_EL1", + "BRBSRC24_EL1", + "BRBSRC25_EL1", + "BRBSRC26_EL1", + "BRBSRC27_EL1", + "BRBSRC28_EL1", + "BRBSRC29_EL1", + "BRBSRC2_EL1", + "BRBSRC30_EL1", + "BRBSRC31_EL1", + "BRBSRC3_EL1", + "BRBSRC4_EL1", + "BRBSRC5_EL1", + "BRBSRC6_EL1", + "BRBSRC7_EL1", + "BRBSRC8_EL1", + "BRBSRC9_EL1", + "BRBSRCINJ_EL1", + "BRBTGT0_EL1", + "BRBTGT10_EL1", + "BRBTGT11_EL1", + "BRBTGT12_EL1", + "BRBTGT13_EL1", + "BRBTGT14_EL1", + "BRBTGT15_EL1", + "BRBTGT16_EL1", + "BRBTGT17_EL1", + "BRBTGT18_EL1", + "BRBTGT19_EL1", + "BRBTGT1_EL1", + "BRBTGT20_EL1", + "BRBTGT21_EL1", + "BRBTGT22_EL1", + "BRBTGT23_EL1", + "BRBTGT24_EL1", + "BRBTGT25_EL1", + "BRBTGT26_EL1", + "BRBTGT27_EL1", + "BRBTGT28_EL1", + "BRBTGT29_EL1", + "BRBTGT2_EL1", + "BRBTGT30_EL1", + "BRBTGT31_EL1", + "BRBTGT3_EL1", + "BRBTGT4_EL1", + "BRBTGT5_EL1", + "BRBTGT6_EL1", + "BRBTGT7_EL1", + "BRBTGT8_EL1", + "BRBTGT9_EL1", + "BRBTGTINJ_EL1", + "BRBTS_EL1", + "CCSIDR2_EL1", + "CCSIDR_EL1", + "CLIDR_EL1", + "CNTFRQ_EL0", + "CNTHCTL_EL2", + "CNTHPS_CTL_EL2", + "CNTHPS_CVAL_EL2", + "CNTHPS_TVAL_EL2", + "CNTHP_CTL_EL2", + "CNTHP_CVAL_EL2", + "CNTHP_TVAL_EL2", + "CNTHVS_CTL_EL2", + "CNTHVS_CVAL_EL2", + "CNTHVS_TVAL_EL2", + "CNTHV_CTL_EL2", + "CNTHV_CVAL_EL2", + "CNTHV_TVAL_EL2", + "CNTISCALE_EL2", + "CNTKCTL_EL1", + "CNTKCTL_EL12", + "CNTPCTSS_EL0", + "CNTPCT_EL0", + "CNTPOFF_EL2", + "CNTPS_CTL_EL1", + "CNTPS_CVAL_EL1", + "CNTPS_TVAL_EL1", + "CNTP_CTL_EL0", + "CNTP_CTL_EL02", + "CNTP_CVAL_EL0", + "CNTP_CVAL_EL02", + "CNTP_TVAL_EL0", + "CNTP_TVAL_EL02", + "CNTSCALE_EL2", + "CNTVCTSS_EL0", + "CNTVCT_EL0", + "CNTVFRQ_EL2", + "CNTVOFF_EL2", + "CNTV_CTL_EL0", + "CNTV_CTL_EL02", + "CNTV_CVAL_EL0", + "CNTV_CVAL_EL02", + "CNTV_TVAL_EL0", + "CNTV_TVAL_EL02", + "CONTEXTIDR_EL1", + "CONTEXTIDR_EL12", + "CONTEXTIDR_EL2", + "CPACR_EL1", + "CPACR_EL12", + "CPTR_EL2", + "CPTR_EL3", + "CSSELR_EL1", + "CTR_EL0", + "CURRENTEL", + "DACR32_EL2", + "DAIF", + "DBGAUTHSTATUS_EL1", + "DBGBCR0_EL1", + "DBGBCR10_EL1", + "DBGBCR11_EL1", + "DBGBCR12_EL1", + "DBGBCR13_EL1", + "DBGBCR14_EL1", + "DBGBCR15_EL1", + "DBGBCR1_EL1", + "DBGBCR2_EL1", + "DBGBCR3_EL1", + "DBGBCR4_EL1", + "DBGBCR5_EL1", + "DBGBCR6_EL1", + "DBGBCR7_EL1", + "DBGBCR8_EL1", + "DBGBCR9_EL1", + "DBGBVR0_EL1", + "DBGBVR10_EL1", + "DBGBVR11_EL1", + "DBGBVR12_EL1", + "DBGBVR13_EL1", + "DBGBVR14_EL1", + "DBGBVR15_EL1", + "DBGBVR1_EL1", + "DBGBVR2_EL1", + "DBGBVR3_EL1", + "DBGBVR4_EL1", + "DBGBVR5_EL1", + "DBGBVR6_EL1", + "DBGBVR7_EL1", + "DBGBVR8_EL1", + "DBGBVR9_EL1", + "DBGCLAIMCLR_EL1", + "DBGCLAIMSET_EL1", + "DBGDTRRX_EL0", + "DBGDTRTX_EL0", + "DBGDTR_EL0", + "DBGPRCR_EL1", + "DBGVCR32_EL2", + "DBGWCR0_EL1", + "DBGWCR10_EL1", + "DBGWCR11_EL1", + "DBGWCR12_EL1", + "DBGWCR13_EL1", + "DBGWCR14_EL1", + "DBGWCR15_EL1", + "DBGWCR1_EL1", + "DBGWCR2_EL1", + "DBGWCR3_EL1", + "DBGWCR4_EL1", + "DBGWCR5_EL1", + "DBGWCR6_EL1", + "DBGWCR7_EL1", + "DBGWCR8_EL1", + "DBGWCR9_EL1", + "DBGWVR0_EL1", + "DBGWVR10_EL1", + "DBGWVR11_EL1", + "DBGWVR12_EL1", + "DBGWVR13_EL1", + "DBGWVR14_EL1", + "DBGWVR15_EL1", + "DBGWVR1_EL1", + "DBGWVR2_EL1", + "DBGWVR3_EL1", + "DBGWVR4_EL1", + "DBGWVR5_EL1", + "DBGWVR6_EL1", + "DBGWVR7_EL1", + "DBGWVR8_EL1", + "DBGWVR9_EL1", + "DCZID_EL0", + "DISR_EL1", + "DIT", + "DLR_EL0", + "DSPSR_EL0", + "ELR_EL1", + "ELR_EL12", + "ELR_EL2", + "ELR_EL3", + "ERRIDR_EL1", + "ERRSELR_EL1", + "ERXADDR_EL1", + "ERXCTLR_EL1", + "ERXFR_EL1", + "ERXGSR_EL1", + "ERXMISC0_EL1", + "ERXMISC1_EL1", + "ERXMISC2_EL1", + "ERXMISC3_EL1", + "ERXPFGCDN_EL1", + "ERXPFGCTL_EL1", + "ERXPFGF_EL1", + "ERXSTATUS_EL1", + "ESR_EL1", + "ESR_EL12", + "ESR_EL2", + "ESR_EL3", + "FAR_EL1", + "FAR_EL12", + "FAR_EL2", + "FAR_EL3", + "FGWTE3_EL3", + "FPCR", + "FPEXC32_EL2", + "FPMR", + "FPSR", + "GCR_EL1", + "GCSCRE0_EL1", + "GCSCR_EL1", + "GCSCR_EL12", + "GCSCR_EL2", + "GCSCR_EL3", + "GCSPR_EL0", + "GCSPR_EL1", + "GCSPR_EL12", + "GCSPR_EL2", + "GCSPR_EL3", + "GMID_EL1", + "GPCCR_EL3", + "GPTBR_EL3", + "HACDBSBR_EL2", + "HACDBSCONS_EL2", + "HACR_EL2", + "HAFGRTR_EL2", + "HCRX_EL2", + "HCR_EL2", + "HDBSSBR_EL2", + "HDBSSPROD_EL2", + "HDFGRTR2_EL2", + "HDFGRTR_EL2", + "HDFGWTR2_EL2", + "HDFGWTR_EL2", + "HFGITR2_EL2", + "HFGITR_EL2", + "HFGRTR2_EL2", + "HFGRTR_EL2", + "HFGWTR2_EL2", + "HFGWTR_EL2", + "HPFAR_EL2", + "HSTR_EL2", + "ICC_AP0R0_EL1", + "ICC_AP0R1_EL1", + "ICC_AP0R2_EL1", + "ICC_AP0R3_EL1", + "ICC_AP1R0_EL1", + "ICC_AP1R1_EL1", + "ICC_AP1R2_EL1", + "ICC_AP1R3_EL1", + "ICC_ASGI1R_EL1", + "ICC_BPR0_EL1", + "ICC_BPR1_EL1", + "ICC_CTLR_EL1", + "ICC_CTLR_EL3", + "ICC_DIR_EL1", + "ICC_EOIR0_EL1", + "ICC_EOIR1_EL1", + "ICC_HPPIR0_EL1", + "ICC_HPPIR1_EL1", + "ICC_IAR0_EL1", + "ICC_IAR1_EL1", + "ICC_IGRPEN0_EL1", + "ICC_IGRPEN1_EL1", + "ICC_IGRPEN1_EL3", + "ICC_NMIAR1_EL1", + "ICC_PMR_EL1", + "ICC_RPR_EL1", + "ICC_SGI0R_EL1", + "ICC_SGI1R_EL1", + "ICC_SRE_EL1", + "ICC_SRE_EL2", + "ICC_SRE_EL3", + "ICH_AP0R0_EL2", + "ICH_AP0R1_EL2", + "ICH_AP0R2_EL2", + "ICH_AP0R3_EL2", + "ICH_AP1R0_EL2", + "ICH_AP1R1_EL2", + "ICH_AP1R2_EL2", + "ICH_AP1R3_EL2", + "ICH_EISR_EL2", + "ICH_ELRSR_EL2", + "ICH_HCR_EL2", + "ICH_LR0_EL2", + "ICH_LR10_EL2", + "ICH_LR11_EL2", + "ICH_LR12_EL2", + "ICH_LR13_EL2", + "ICH_LR14_EL2", + "ICH_LR15_EL2", + "ICH_LR1_EL2", + "ICH_LR2_EL2", + "ICH_LR3_EL2", + "ICH_LR4_EL2", + "ICH_LR5_EL2", + "ICH_LR6_EL2", + "ICH_LR7_EL2", + "ICH_LR8_EL2", + "ICH_LR9_EL2", + "ICH_MISR_EL2", + "ICH_VMCR_EL2", + "ICH_VTR_EL2", + "ID_AA64AFR0_EL1", + "ID_AA64AFR1_EL1", + "ID_AA64DFR0_EL1", + "ID_AA64DFR1_EL1", + "ID_AA64DFR2_EL1", + "ID_AA64FPFR0_EL1", + "ID_AA64ISAR0_EL1", + "ID_AA64ISAR1_EL1", + "ID_AA64ISAR2_EL1", + "ID_AA64ISAR3_EL1", + "ID_AA64MMFR0_EL1", + "ID_AA64MMFR1_EL1", + "ID_AA64MMFR2_EL1", + "ID_AA64MMFR3_EL1", + "ID_AA64MMFR4_EL1", + "ID_AA64PFR0_EL1", + "ID_AA64PFR1_EL1", + "ID_AA64PFR2_EL1", + "ID_AA64SMFR0_EL1", + "ID_AA64ZFR0_EL1", + "ID_AFR0_EL1", + "ID_DFR0_EL1", + "ID_DFR1_EL1", + "ID_ISAR0_EL1", + "ID_ISAR1_EL1", + "ID_ISAR2_EL1", + "ID_ISAR3_EL1", + "ID_ISAR4_EL1", + "ID_ISAR5_EL1", + "ID_ISAR6_EL1", + "ID_MMFR0_EL1", + "ID_MMFR1_EL1", + "ID_MMFR2_EL1", + "ID_MMFR3_EL1", + "ID_MMFR4_EL1", + "ID_MMFR5_EL1", + "ID_PFR0_EL1", + "ID_PFR1_EL1", + "ID_PFR2_EL1", + "IFSR32_EL2", + "ISR_EL1", + "LORC_EL1", + "LOREA_EL1", + "LORID_EL1", + "LORN_EL1", + "LORSA_EL1", + "MAIR2_EL1", + "MAIR2_EL12", + "MAIR2_EL2", + "MAIR2_EL3", + "MAIR_EL1", + "MAIR_EL12", + "MAIR_EL2", + "MAIR_EL3", + "MDCCINT_EL1", + "MDCCSR_EL0", + "MDCR_EL2", + "MDCR_EL3", + "MDRAR_EL1", + "MDSCR_EL1", + "MDSELR_EL1", + "MDSTEPOP_EL1", + "MECIDR_EL2", + "MECID_A0_EL2", + "MECID_A1_EL2", + "MECID_P0_EL2", + "MECID_P1_EL2", + "MECID_RL_A_EL3", + "MFAR_EL3", + "MIDR_EL1", + "MPAM0_EL1", + "MPAM1_EL1", + "MPAM1_EL12", + "MPAM2_EL2", + "MPAM3_EL3", + "MPAMHCR_EL2", + "MPAMIDR_EL1", + "MPAMSM_EL1", + "MPAMVPM0_EL2", + "MPAMVPM1_EL2", + "MPAMVPM2_EL2", + "MPAMVPM3_EL2", + "MPAMVPM4_EL2", + "MPAMVPM5_EL2", + "MPAMVPM6_EL2", + "MPAMVPM7_EL2", + "MPAMVPMV_EL2", + "MPIDR_EL1", + "MPUIR_EL1", + "MPUIR_EL2", + "MVFR0_EL1", + "MVFR1_EL1", + "MVFR2_EL1", + "NZCV", + "OSDLR_EL1", + "OSDTRRX_EL1", + "OSDTRTX_EL1", + "OSECCR_EL1", + "OSLAR_EL1", + "OSLSR_EL1", + "PAN", + "PAR_EL1", + "PFAR_EL1", + "PFAR_EL12", + "PFAR_EL2", + "PIRE0_EL1", + "PIRE0_EL12", + "PIRE0_EL2", + "PIR_EL1", + "PIR_EL12", + "PIR_EL2", + "PIR_EL3", + "PM", + "PMBIDR_EL1", + "PMBLIMITR_EL1", + "PMBPTR_EL1", + "PMBSR_EL1", + "PMCCFILTR_EL0", + "PMCCNTR_EL0", + "PMCCNTSVR_EL1", + "PMCEID0_EL0", + "PMCEID1_EL0", + "PMCNTENCLR_EL0", + "PMCNTENSET_EL0", + "PMCR_EL0", + "PMECR_EL1", + "PMEVCNTR0_EL0", + "PMEVCNTR10_EL0", + "PMEVCNTR11_EL0", + "PMEVCNTR12_EL0", + "PMEVCNTR13_EL0", + "PMEVCNTR14_EL0", + "PMEVCNTR15_EL0", + "PMEVCNTR16_EL0", + "PMEVCNTR17_EL0", + "PMEVCNTR18_EL0", + "PMEVCNTR19_EL0", + "PMEVCNTR1_EL0", + "PMEVCNTR20_EL0", + "PMEVCNTR21_EL0", + "PMEVCNTR22_EL0", + "PMEVCNTR23_EL0", + "PMEVCNTR24_EL0", + "PMEVCNTR25_EL0", + "PMEVCNTR26_EL0", + "PMEVCNTR27_EL0", + "PMEVCNTR28_EL0", + "PMEVCNTR29_EL0", + "PMEVCNTR2_EL0", + "PMEVCNTR30_EL0", + "PMEVCNTR3_EL0", + "PMEVCNTR4_EL0", + "PMEVCNTR5_EL0", + "PMEVCNTR6_EL0", + "PMEVCNTR7_EL0", + "PMEVCNTR8_EL0", + "PMEVCNTR9_EL0", + "PMEVCNTSVR0_EL1", + "PMEVCNTSVR10_EL1", + "PMEVCNTSVR11_EL1", + "PMEVCNTSVR12_EL1", + "PMEVCNTSVR13_EL1", + "PMEVCNTSVR14_EL1", + "PMEVCNTSVR15_EL1", + "PMEVCNTSVR16_EL1", + "PMEVCNTSVR17_EL1", + "PMEVCNTSVR18_EL1", + "PMEVCNTSVR19_EL1", + "PMEVCNTSVR1_EL1", + "PMEVCNTSVR20_EL1", + "PMEVCNTSVR21_EL1", + "PMEVCNTSVR22_EL1", + "PMEVCNTSVR23_EL1", + "PMEVCNTSVR24_EL1", + "PMEVCNTSVR25_EL1", + "PMEVCNTSVR26_EL1", + "PMEVCNTSVR27_EL1", + "PMEVCNTSVR28_EL1", + "PMEVCNTSVR29_EL1", + "PMEVCNTSVR2_EL1", + "PMEVCNTSVR30_EL1", + "PMEVCNTSVR3_EL1", + "PMEVCNTSVR4_EL1", + "PMEVCNTSVR5_EL1", + "PMEVCNTSVR6_EL1", + "PMEVCNTSVR7_EL1", + "PMEVCNTSVR8_EL1", + "PMEVCNTSVR9_EL1", + "PMEVTYPER0_EL0", + "PMEVTYPER10_EL0", + "PMEVTYPER11_EL0", + "PMEVTYPER12_EL0", + "PMEVTYPER13_EL0", + "PMEVTYPER14_EL0", + "PMEVTYPER15_EL0", + "PMEVTYPER16_EL0", + "PMEVTYPER17_EL0", + "PMEVTYPER18_EL0", + "PMEVTYPER19_EL0", + "PMEVTYPER1_EL0", + "PMEVTYPER20_EL0", + "PMEVTYPER21_EL0", + "PMEVTYPER22_EL0", + "PMEVTYPER23_EL0", + "PMEVTYPER24_EL0", + "PMEVTYPER25_EL0", + "PMEVTYPER26_EL0", + "PMEVTYPER27_EL0", + "PMEVTYPER28_EL0", + "PMEVTYPER29_EL0", + "PMEVTYPER2_EL0", + "PMEVTYPER30_EL0", + "PMEVTYPER3_EL0", + "PMEVTYPER4_EL0", + "PMEVTYPER5_EL0", + "PMEVTYPER6_EL0", + "PMEVTYPER7_EL0", + "PMEVTYPER8_EL0", + "PMEVTYPER9_EL0", + "PMIAR_EL1", + "PMICFILTR_EL0", + "PMICNTR_EL0", + "PMICNTSVR_EL1", + "PMINTENCLR_EL1", + "PMINTENSET_EL1", + "PMMIR_EL1", + "PMOVSCLR_EL0", + "PMOVSSET_EL0", + "PMSCR_EL1", + "PMSCR_EL12", + "PMSCR_EL2", + "PMSDSFR_EL1", + "PMSELR_EL0", + "PMSEVFR_EL1", + "PMSFCR_EL1", + "PMSICR_EL1", + "PMSIDR_EL1", + "PMSIRR_EL1", + "PMSLATFR_EL1", + "PMSNEVFR_EL1", + "PMSSCR_EL1", + "PMSWINC_EL0", + "PMUACR_EL1", + "PMUSERENR_EL0", + "PMXEVCNTR_EL0", + "PMXEVTYPER_EL0", + "PMZR_EL0", + "POR_EL0", + "POR_EL1", + "POR_EL12", + "POR_EL2", + "POR_EL3", + "PRBAR10_EL1", + "PRBAR10_EL2", + "PRBAR11_EL1", + "PRBAR11_EL2", + "PRBAR12_EL1", + "PRBAR12_EL2", + "PRBAR13_EL1", + "PRBAR13_EL2", + "PRBAR14_EL1", + "PRBAR14_EL2", + "PRBAR15_EL1", + "PRBAR15_EL2", + "PRBAR1_EL1", + "PRBAR1_EL2", + "PRBAR2_EL1", + "PRBAR2_EL2", + "PRBAR3_EL1", + "PRBAR3_EL2", + "PRBAR4_EL1", + "PRBAR4_EL2", + "PRBAR5_EL1", + "PRBAR5_EL2", + "PRBAR6_EL1", + "PRBAR6_EL2", + "PRBAR7_EL1", + "PRBAR7_EL2", + "PRBAR8_EL1", + "PRBAR8_EL2", + "PRBAR9_EL1", + "PRBAR9_EL2", + "PRBAR_EL1", + "PRBAR_EL2", + "PRENR_EL1", + "PRENR_EL2", + "PRLAR10_EL1", + "PRLAR10_EL2", + "PRLAR11_EL1", + "PRLAR11_EL2", + "PRLAR12_EL1", + "PRLAR12_EL2", + "PRLAR13_EL1", + "PRLAR13_EL2", + "PRLAR14_EL1", + "PRLAR14_EL2", + "PRLAR15_EL1", + "PRLAR15_EL2", + "PRLAR1_EL1", + "PRLAR1_EL2", + "PRLAR2_EL1", + "PRLAR2_EL2", + "PRLAR3_EL1", + "PRLAR3_EL2", + "PRLAR4_EL1", + "PRLAR4_EL2", + "PRLAR5_EL1", + "PRLAR5_EL2", + "PRLAR6_EL1", + "PRLAR6_EL2", + "PRLAR7_EL1", + "PRLAR7_EL2", + "PRLAR8_EL1", + "PRLAR8_EL2", + "PRLAR9_EL1", + "PRLAR9_EL2", + "PRLAR_EL1", + "PRLAR_EL2", + "PRSELR_EL1", + "PRSELR_EL2", + "RCWMASK_EL1", + "RCWSMASK_EL1", + "REVIDR_EL1", + "RGSR_EL1", + "RMR_EL1", + "RMR_EL2", + "RMR_EL3", + "RNDR", + "RNDRRS", + "RVBAR_EL1", + "RVBAR_EL2", + "RVBAR_EL3", + "S2PIR_EL2", + "S2POR_EL1", + "SCR_EL3", + "SCTLR2_EL1", + "SCTLR2_EL12", + "SCTLR2_EL2", + "SCTLR2_EL3", + "SCTLR_EL1", + "SCTLR_EL12", + "SCTLR_EL2", + "SCTLR_EL3", + "SCXTNUM_EL0", + "SCXTNUM_EL1", + "SCXTNUM_EL12", + "SCXTNUM_EL2", + "SCXTNUM_EL3", + "SDER32_EL2", + "SDER32_EL3", + "SMCR_EL1", + "SMCR_EL12", + "SMCR_EL2", + "SMCR_EL3", + "SMIDR_EL1", + "SMPRIMAP_EL2", + "SMPRI_EL1", + "SPMACCESSR_EL1", + "SPMACCESSR_EL12", + "SPMACCESSR_EL2", + "SPMACCESSR_EL3", + "SPMCFGR_EL1", + "SPMCGCR0_EL1", + "SPMCGCR1_EL1", + "SPMCNTENCLR_EL0", + "SPMCNTENSET_EL0", + "SPMCR_EL0", + "SPMDEVAFF_EL1", + "SPMDEVARCH_EL1", + "SPMEVCNTR0_EL0", + "SPMEVCNTR10_EL0", + "SPMEVCNTR11_EL0", + "SPMEVCNTR12_EL0", + "SPMEVCNTR13_EL0", + "SPMEVCNTR14_EL0", + "SPMEVCNTR15_EL0", + "SPMEVCNTR1_EL0", + "SPMEVCNTR2_EL0", + "SPMEVCNTR3_EL0", + "SPMEVCNTR4_EL0", + "SPMEVCNTR5_EL0", + "SPMEVCNTR6_EL0", + "SPMEVCNTR7_EL0", + "SPMEVCNTR8_EL0", + "SPMEVCNTR9_EL0", + "SPMEVFILT2R0_EL0", + "SPMEVFILT2R10_EL0", + "SPMEVFILT2R11_EL0", + "SPMEVFILT2R12_EL0", + "SPMEVFILT2R13_EL0", + "SPMEVFILT2R14_EL0", + "SPMEVFILT2R15_EL0", + "SPMEVFILT2R1_EL0", + "SPMEVFILT2R2_EL0", + "SPMEVFILT2R3_EL0", + "SPMEVFILT2R4_EL0", + "SPMEVFILT2R5_EL0", + "SPMEVFILT2R6_EL0", + "SPMEVFILT2R7_EL0", + "SPMEVFILT2R8_EL0", + "SPMEVFILT2R9_EL0", + "SPMEVFILTR0_EL0", + "SPMEVFILTR10_EL0", + "SPMEVFILTR11_EL0", + "SPMEVFILTR12_EL0", + "SPMEVFILTR13_EL0", + "SPMEVFILTR14_EL0", + "SPMEVFILTR15_EL0", + "SPMEVFILTR1_EL0", + "SPMEVFILTR2_EL0", + "SPMEVFILTR3_EL0", + "SPMEVFILTR4_EL0", + "SPMEVFILTR5_EL0", + "SPMEVFILTR6_EL0", + "SPMEVFILTR7_EL0", + "SPMEVFILTR8_EL0", + "SPMEVFILTR9_EL0", + "SPMEVTYPER0_EL0", + "SPMEVTYPER10_EL0", + "SPMEVTYPER11_EL0", + "SPMEVTYPER12_EL0", + "SPMEVTYPER13_EL0", + "SPMEVTYPER14_EL0", + "SPMEVTYPER15_EL0", + "SPMEVTYPER1_EL0", + "SPMEVTYPER2_EL0", + "SPMEVTYPER3_EL0", + "SPMEVTYPER4_EL0", + "SPMEVTYPER5_EL0", + "SPMEVTYPER6_EL0", + "SPMEVTYPER7_EL0", + "SPMEVTYPER8_EL0", + "SPMEVTYPER9_EL0", + "SPMIIDR_EL1", + "SPMINTENCLR_EL1", + "SPMINTENSET_EL1", + "SPMOVSCLR_EL0", + "SPMOVSSET_EL0", + "SPMROOTCR_EL3", + "SPMSCR_EL1", + "SPMSELR_EL0", + "SPMZR_EL0", + "SPSEL", + "SPSR_ABT", + "SPSR_EL1", + "SPSR_EL12", + "SPSR_EL2", + "SPSR_EL3", + "SPSR_FIQ", + "SPSR_IRQ", + "SPSR_UND", + "SP_EL0", + "SP_EL1", + "SP_EL2", + "SSBS", + "SVCR", + "TCO", + "TCR2_EL1", + "TCR2_EL12", + "TCR2_EL2", + "TCR_EL1", + "TCR_EL12", + "TCR_EL2", + "TCR_EL3", + "TEECR32_EL1", + "TEEHBR32_EL1", + "TFSRE0_EL1", + "TFSR_EL1", + "TFSR_EL12", + "TFSR_EL2", + "TFSR_EL3", + "TPIDR2_EL0", + "TPIDRRO_EL0", + "TPIDR_EL0", + "TPIDR_EL1", + "TPIDR_EL2", + "TPIDR_EL3", + "TRBBASER_EL1", + "TRBIDR_EL1", + "TRBLIMITR_EL1", + "TRBMAR_EL1", + "TRBMPAM_EL1", + "TRBPTR_EL1", + "TRBSR_EL1", + "TRBTRG_EL1", + "TRCACATR0", + "TRCACATR1", + "TRCACATR10", + "TRCACATR11", + "TRCACATR12", + "TRCACATR13", + "TRCACATR14", + "TRCACATR15", + "TRCACATR2", + "TRCACATR3", + "TRCACATR4", + "TRCACATR5", + "TRCACATR6", + "TRCACATR7", + "TRCACATR8", + "TRCACATR9", + "TRCACVR0", + "TRCACVR1", + "TRCACVR10", + "TRCACVR11", + "TRCACVR12", + "TRCACVR13", + "TRCACVR14", + "TRCACVR15", + "TRCACVR2", + "TRCACVR3", + "TRCACVR4", + "TRCACVR5", + "TRCACVR6", + "TRCACVR7", + "TRCACVR8", + "TRCACVR9", + "TRCAUTHSTATUS", + "TRCAUXCTLR", + "TRCBBCTLR", + "TRCCCCTLR", + "TRCCIDCCTLR0", + "TRCCIDCCTLR1", + "TRCCIDCVR0", + "TRCCIDCVR1", + "TRCCIDCVR2", + "TRCCIDCVR3", + "TRCCIDCVR4", + "TRCCIDCVR5", + "TRCCIDCVR6", + "TRCCIDCVR7", + "TRCCIDR0", + "TRCCIDR1", + "TRCCIDR2", + "TRCCIDR3", + "TRCCLAIMCLR", + "TRCCLAIMSET", + "TRCCNTCTLR0", + "TRCCNTCTLR1", + "TRCCNTCTLR2", + "TRCCNTCTLR3", + "TRCCNTRLDVR0", + "TRCCNTRLDVR1", + "TRCCNTRLDVR2", + "TRCCNTRLDVR3", + "TRCCNTVR0", + "TRCCNTVR1", + "TRCCNTVR2", + "TRCCNTVR3", + "TRCCONFIGR", + "TRCDEVAFF0", + "TRCDEVAFF1", + "TRCDEVARCH", + "TRCDEVID", + "TRCDEVTYPE", + "TRCDVCMR0", + "TRCDVCMR1", + "TRCDVCMR2", + "TRCDVCMR3", + "TRCDVCMR4", + "TRCDVCMR5", + "TRCDVCMR6", + "TRCDVCMR7", + "TRCDVCVR0", + "TRCDVCVR1", + "TRCDVCVR2", + "TRCDVCVR3", + "TRCDVCVR4", + "TRCDVCVR5", + "TRCDVCVR6", + "TRCDVCVR7", + "TRCEVENTCTL0R", + "TRCEVENTCTL1R", + "TRCEXTINSELR", + "TRCEXTINSELR0", + "TRCEXTINSELR1", + "TRCEXTINSELR2", + "TRCEXTINSELR3", + "TRCIDR0", + "TRCIDR1", + "TRCIDR10", + "TRCIDR11", + "TRCIDR12", + "TRCIDR13", + "TRCIDR2", + "TRCIDR3", + "TRCIDR4", + "TRCIDR5", + "TRCIDR6", + "TRCIDR7", + "TRCIDR8", + "TRCIDR9", + "TRCIMSPEC0", + "TRCIMSPEC1", + "TRCIMSPEC2", + "TRCIMSPEC3", + "TRCIMSPEC4", + "TRCIMSPEC5", + "TRCIMSPEC6", + "TRCIMSPEC7", + "TRCITCTRL", + "TRCITECR_EL1", + "TRCITECR_EL12", + "TRCITECR_EL2", + "TRCITEEDCR", + "TRCLAR", + "TRCLSR", + "TRCOSLAR", + "TRCOSLSR", + "TRCPDCR", + "TRCPDSR", + "TRCPIDR0", + "TRCPIDR1", + "TRCPIDR2", + "TRCPIDR3", + "TRCPIDR4", + "TRCPIDR5", + "TRCPIDR6", + "TRCPIDR7", + "TRCPRGCTLR", + "TRCPROCSELR", + "TRCQCTLR", + "TRCRSCTLR10", + "TRCRSCTLR11", + "TRCRSCTLR12", + "TRCRSCTLR13", + "TRCRSCTLR14", + "TRCRSCTLR15", + "TRCRSCTLR16", + "TRCRSCTLR17", + "TRCRSCTLR18", + "TRCRSCTLR19", + "TRCRSCTLR2", + "TRCRSCTLR20", + "TRCRSCTLR21", + "TRCRSCTLR22", + "TRCRSCTLR23", + "TRCRSCTLR24", + "TRCRSCTLR25", + "TRCRSCTLR26", + "TRCRSCTLR27", + "TRCRSCTLR28", + "TRCRSCTLR29", + "TRCRSCTLR3", + "TRCRSCTLR30", + "TRCRSCTLR31", + "TRCRSCTLR4", + "TRCRSCTLR5", + "TRCRSCTLR6", + "TRCRSCTLR7", + "TRCRSCTLR8", + "TRCRSCTLR9", + "TRCRSR", + "TRCSEQEVR0", + "TRCSEQEVR1", + "TRCSEQEVR2", + "TRCSEQRSTEVR", + "TRCSEQSTR", + "TRCSSCCR0", + "TRCSSCCR1", + "TRCSSCCR2", + "TRCSSCCR3", + "TRCSSCCR4", + "TRCSSCCR5", + "TRCSSCCR6", + "TRCSSCCR7", + "TRCSSCSR0", + "TRCSSCSR1", + "TRCSSCSR2", + "TRCSSCSR3", + "TRCSSCSR4", + "TRCSSCSR5", + "TRCSSCSR6", + "TRCSSCSR7", + "TRCSSPCICR0", + "TRCSSPCICR1", + "TRCSSPCICR2", + "TRCSSPCICR3", + "TRCSSPCICR4", + "TRCSSPCICR5", + "TRCSSPCICR6", + "TRCSSPCICR7", + "TRCSTALLCTLR", + "TRCSTATR", + "TRCSYNCPR", + "TRCTRACEIDR", + "TRCTSCTLR", + "TRCVDARCCTLR", + "TRCVDCTLR", + "TRCVDSACCTLR", + "TRCVICTLR", + "TRCVIIECTLR", + "TRCVIPCSSCTLR", + "TRCVISSCTLR", + "TRCVMIDCCTLR0", + "TRCVMIDCCTLR1", + "TRCVMIDCVR0", + "TRCVMIDCVR1", + "TRCVMIDCVR2", + "TRCVMIDCVR3", + "TRCVMIDCVR4", + "TRCVMIDCVR5", + "TRCVMIDCVR6", + "TRCVMIDCVR7", + "TRFCR_EL1", + "TRFCR_EL12", + "TRFCR_EL2", + "TTBR0_EL1", + "TTBR0_EL12", + "TTBR0_EL2", + "TTBR0_EL3", + "TTBR1_EL1", + "TTBR1_EL12", + "TTBR1_EL2", + "UAO", + "VBAR_EL1", + "VBAR_EL12", + "VBAR_EL2", + "VBAR_EL3", + "VDISR_EL2", + "VDISR_EL3", + "VMECID_A_EL2", + "VMECID_P_EL2", + "VMPIDR_EL2", + "VNCR_EL2", + "VPIDR_EL2", + "VSCTLR_EL2", + "VSESR_EL2", + "VSESR_EL3", + "VSTCR_EL2", + "VSTTBR_EL2", + "VTCR_EL2", + "VTTBR_EL2", + "ZCR_EL1", + "ZCR_EL12", + "ZCR_EL2", + "ZCR_EL3", +}; const char *const AArch64TargetInfo::GCCRegNames[] = { // clang-format off @@ -1283,6 +2498,10 @@ ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { return llvm::ArrayRef(GCCRegNames); } +ArrayRef<const char *> AArch64TargetInfo::getSystemRegNames() const { + return llvm::ArrayRef(SystemRegNames); +} + const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { {{"w31"}, "wsp"}, {{"x31"}, "sp"}, diff --git a/clang/lib/Basic/Targets/AArch64.h b/clang/lib/Basic/Targets/AArch64.h index 7bdf5a2b4106e4..f794a9139e06c1 100644 --- a/clang/lib/Basic/Targets/AArch64.h +++ b/clang/lib/Basic/Targets/AArch64.h @@ -25,6 +25,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo { virtual void setDataLayout() = 0; static const TargetInfo::GCCRegAlias GCCRegAliases[]; static const char *const GCCRegNames[]; + static const char *const SystemRegNames[]; enum FPUModeEnum { FPUMode = (1 << 0), @@ -175,6 +176,8 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo { ArrayRef<const char *> getGCCRegNames() const override; ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; + ArrayRef<const char *> getSystemRegNames() const override; + std::string convertConstraint(const char *&Constraint) const override; bool validateAsmConstraint(const char *&Name, diff --git a/clang/lib/Sema/SemaARM.cpp b/clang/lib/Sema/SemaARM.cpp index d8dd4fe16e3af0..e4077d62742427 100644 --- a/clang/lib/Sema/SemaARM.cpp +++ b/clang/lib/Sema/SemaARM.cpp @@ -16,6 +16,7 @@ #include "clang/Sema/Initialization.h" #include "clang/Sema/ParsedAttr.h" #include "clang/Sema/Sema.h" +#include "llvm/Support/Regex.h" namespace clang { @@ -184,9 +185,9 @@ bool SemaARM::BuiltinARMMemoryTaggingCall(unsigned BuiltinID, /// BuiltinARMSpecialReg - Handle a check if argument ArgNum of CallExpr /// TheCall is an ARM/AArch64 special register string literal. -bool SemaARM::BuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall, - int ArgNum, unsigned ExpectedFieldNum, - bool AllowName) { +bool SemaARM::BuiltinARMSpecialReg(const TargetInfo &TI, unsigned BuiltinID, + CallExpr *TheCall, int ArgNum, + unsigned ExpectedFieldNum, bool AllowName) { bool IsARMBuiltin = BuiltinID == ARM::BI__builtin_arm_rsr64 || BuiltinID == ARM::BI__builtin_arm_wsr64 || BuiltinID == ARM::BI__builtin_arm_rsr || @@ -205,13 +206,17 @@ bool SemaARM::BuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall, // We can't check the value of a dependent argument. Expr *Arg = TheCall->getArg(ArgNum); + + auto CreateDiagErr = [&](unsigned DiagID) { + return Diag(TheCall->getBeginLoc(), DiagID) << Arg->getSourceRange(); + }; + if (Arg->isTypeDependent() || Arg->isValueDependent()) return false; // Check if the argument is a string literal. if (!isa<StringLiteral>(Arg->IgnoreParenImpCasts())) - return Diag(TheCall->getBeginLoc(), diag::err_expr_not_string_literal) - << Arg->getSourceRange(); + return CreateDiagErr(diag::err_expr_not_string_literal); // Check the type of special register given. StringRef Reg = cast<StringLiteral>(Arg->IgnoreParenImpCasts())->getString(); @@ -219,8 +224,7 @@ bool SemaARM::BuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall, Reg.split(Fields, ":"); if (Fields.size() != ExpectedFieldNum && !(AllowName && Fields.size() == 1)) - return Diag(TheCall->getBeginLoc(), diag::err_arm_invalid_specialreg) - << Arg->getSourceRange(); + return CreateDiagErr(diag::err_arm_invalid_specialreg); // If the string is the name of a register then we cannot check that it is // valid here but if the string is of one the forms described in ACLE then we @@ -261,19 +265,26 @@ bool SemaARM::BuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall, } if (!ValidString) - return Diag(TheCall->getBeginLoc(), diag::err_arm_invalid_specialreg) - << Arg->getSourceRange(); + return CreateDiagErr(diag::err_arm_invalid_specialreg); + } else if (IsAArch64Builtin && Fields.size() == 1) { // This code validates writes to PSTATE registers. - // Not a write. - if (TheCall->getNumArgs() != 2) - return false; + { + // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name + static const llvm::Regex GenericRegPattern( + "^S([0-3])_([0-7])_C([0-9]|1[0-5])_C([0-9]|1[0-5])_([0-7])$"); + if (GenericRegPattern.match(Reg.upper())) + return false; + } + + if (TheCall->getNumArgs() != 2 || // Not a write. - // The 128-bit system register accesses do not touch PSTATE. - if (BuiltinID == AArch64::BI__builtin_arm_rsr128 || + // The 128-bit system register accesses do not touch PSTATE. + BuiltinID == AArch64::BI__builtin_arm_rsr128 || BuiltinID == AArch64::BI__builtin_arm_wsr128) - return false; + return !TI.isValidSystemRegisterName(Reg) && + CreateDiagErr(diag::err_arm_invalid_specialreg); // These are the named PSTATE accesses using "MSR (immediate)" instructions, // along with the upper limit on the immediates allowed. @@ -293,7 +304,8 @@ bool SemaARM::BuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall, // If this is not a named PSTATE, just continue without validating, as this // will be lowered to an "MSR (register)" instruction directly if (!MaxLimit) - return false; + return !TI.isValidSystemRegisterName(Reg) && + CreateDiagErr(diag::err_arm_invalid_specialreg); // Here we only allow constants in the range for that pstate, as required by // the ACLE. @@ -999,13 +1011,13 @@ bool SemaARM::CheckARMBuiltinFunctionCall(const TargetInfo &TI, if (BuiltinID == ARM::BI__builtin_arm_rsr64 || BuiltinID == ARM::BI__builtin_arm_wsr64) - return BuiltinARMSpecialReg(BuiltinID, TheCall, 0, 3, false); + return BuiltinARMSpecialReg(TI, BuiltinID, TheCall, 0, 3, false); if (BuiltinID == ARM::BI__builtin_arm_rsr || BuiltinID == ARM::BI__builtin_arm_rsrp || BuiltinID == ARM::BI__builtin_arm_wsr || BuiltinID == ARM::BI__builtin_arm_wsrp) - return BuiltinARMSpecialReg(BuiltinID, TheCall, 0, 5, true); + return BuiltinARMSpecialReg(TI, BuiltinID, TheCall, 0, 5, true); if (CheckNeonBuiltinFunctionCall(TI, BuiltinID, TheCall)) return true; @@ -1081,7 +1093,7 @@ bool SemaARM::CheckAArch64BuiltinFunctionCall(const TargetInfo &TI, BuiltinID == AArch64::BI__builtin_arm_wsr64 || BuiltinID == AArch64::BI__builtin_arm_rsr128 || BuiltinID == AArch64::BI__builtin_arm_wsr128) - return BuiltinARMSpecialReg(BuiltinID, TheCall, 0, 5, true); + return BuiltinARMSpecialReg(TI, BuiltinID, TheCall, 0, 5, true); // Memory Tagging Extensions (MTE) Intrinsics if (BuiltinID == AArch64::BI__builtin_arm_irg || @@ -1097,7 +1109,7 @@ bool SemaARM::CheckAArch64BuiltinFunctionCall(const TargetInfo &TI, BuiltinID == AArch64::BI__builtin_arm_rsrp || BuiltinID == AArch64::BI__builtin_arm_wsr || BuiltinID == AArch64::BI__builtin_arm_wsrp) - return BuiltinARMSpecialReg(BuiltinID, TheCall, 0, 5, true); + return BuiltinARMSpecialReg(TI, BuiltinID, TheCall, 0, 5, true); // Only check the valid encoding range. Any constant in this range would be // converted to a register of the form S1_2_C3_C4_5. Let the hardware throw diff --git a/clang/test/Sema/aarch64-special-register.c b/clang/test/Sema/aarch64-special-register.c index 4d2cfd8b37c847..2c56bf030ca436 100644 --- a/clang/test/Sema/aarch64-special-register.c +++ b/clang/test/Sema/aarch64-special-register.c @@ -5,35 +5,35 @@ void string_literal(unsigned v) { } void wsr_1(unsigned v) { - __builtin_arm_wsr("sysreg", v); + __builtin_arm_wsr("aidr_el1", v); } void wsrp_1(void *v) { - __builtin_arm_wsrp("sysreg", v); + __builtin_arm_wsrp("aidr_el1", v); } void wsr64_1(unsigned long v) { - __builtin_arm_wsr64("sysreg", v); + __builtin_arm_wsr64("aidr_el1", v); } void wsr128_1(__uint128_t v) { - __builtin_arm_wsr128("sysreg", v); + __builtin_arm_wsr128("aidr_el1", v); } unsigned rsr_1(void) { - return __builtin_arm_rsr("sysreg"); + return __builtin_arm_rsr("aidr_el1"); } void *rsrp_1(void) { - return __builtin_arm_rsrp("sysreg"); + return __builtin_arm_rsrp("aidr_el1"); } unsigned long rsr64_1(void) { - return __builtin_arm_rsr64("sysreg"); + return __builtin_arm_rsr64("aidr_el1"); } __uint128_t rsr128_1(void) { - return __builtin_arm_rsr128("sysreg"); + return __builtin_arm_rsr128("aidr_el1"); } void wsr_2(unsigned v) { @@ -213,3 +213,10 @@ void wsr64_6(void) { __builtin_arm_wsr64("allint", 2); // expected-error {{outside the valid range}} __builtin_arm_wsr64("pm", 2); // expected-error {{outside the valid range}} } + +void sysreg_invalid_name(unsigned long *r) { + r[0] = __builtin_arm_rsr("sysreg"); //expected-error {{invalid special register for builtin}} + r[1] = __builtin_arm_rsr64("sysreg"); //expected-error {{invalid special register for builtin}} + __builtin_arm_wsr64("sysreg", r[3]); //expected-error {{invalid special register for builtin}} + __builtin_arm_wsr64("sysreg", r[4]); //expected-error {{invalid special register for builtin}} +} _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
