https://github.com/v01dXYZ created https://github.com/llvm/llvm-project/pull/105608
The range for Op0 was set to 1 instead of 3. The description of e493f177eeee84a9c6000ca7c92499233490f1d1 visually explains the encoding of implementation-defined system registers. Gobolt: https://godbolt.org/z/WK9PqPvGE (comment out the last one to convince yourself they represent the same system register). >From 4abe7a1a5bc295b2cdd4f69ad606b6051401404e Mon Sep 17 00:00:00 2001 From: v01dxyz <v01d...@v01d.xyz> Date: Thu, 22 Aug 2024 03:55:27 +0200 Subject: [PATCH] [Clang][AArch64] Fix typo with colon-separated syntax for system registers The range for Op0 was set to 1 instead of 3. Since the ranges are all power of 2 minus 1, this commit reformulates them with the bitwidth of each part of the register to highlight the association with the encoding. cf one commit description explaining the encoding of an implementation-defined system register: e493f177eeee84a9c6000ca7c92499233490f1d1 --- clang/lib/Sema/SemaARM.cpp | 8 ++++---- clang/test/Sema/aarch64-special-register.c | 7 +++++++ 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/clang/lib/Sema/SemaARM.cpp b/clang/lib/Sema/SemaARM.cpp index d8dd4fe16e3af0..cb53c61aa857d7 100644 --- a/clang/lib/Sema/SemaARM.cpp +++ b/clang/lib/Sema/SemaARM.cpp @@ -248,16 +248,16 @@ bool SemaARM::BuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall, } } - SmallVector<int, 5> Ranges; + SmallVector<int, 5> FieldBitWidths; if (FiveFields) - Ranges.append({IsAArch64Builtin ? 1 : 15, 7, 15, 15, 7}); + FieldBitWidths.append({IsAArch64Builtin ? 2 : 4, 3, 4, 4, 3}); else - Ranges.append({15, 7, 15}); + FieldBitWidths.append({4, 3, 4}); for (unsigned i = 0; i < Fields.size(); ++i) { int IntField; ValidString &= !Fields[i].getAsInteger(10, IntField); - ValidString &= (IntField >= 0 && IntField <= Ranges[i]); + ValidString &= (IntField >= 0 && IntField < (1 << FieldBitWidths[i])); } if (!ValidString) diff --git a/clang/test/Sema/aarch64-special-register.c b/clang/test/Sema/aarch64-special-register.c index 4d2cfd8b37c847..53a2c32b84777c 100644 --- a/clang/test/Sema/aarch64-special-register.c +++ b/clang/test/Sema/aarch64-special-register.c @@ -116,6 +116,13 @@ unsigned long rsr64_6(void) { return __builtin_arm_rsr64("0:1:16:16:2"); //expected-error {{invalid special register for builtin}} } +void rsr64_7(unsigned long *r) { + // the following three instructions should produce the same assembly + r[0] = __builtin_arm_rsr64("ICC_CTLR_EL3"); + r[1] = __builtin_arm_rsr64("s3_6_c12_c12_4"); + r[2] = __builtin_arm_rsr64("3:6:12:12:4"); +} + __uint128_t rsr128_3(void) { return __builtin_arm_rsr128("0:1:2"); //expected-error {{invalid special register for builtin}} } _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
