================
@@ -1959,9 +2064,12 @@ multiclass VCMLA_ROTS<string type, string lanety, string
laneqty> {
let isLaneQ = 1 in {
// vcmla{ROT}_laneq
+ // ACLE specifies that the fp16 vcmla_#ROT_laneq variant has an
immedaite range of 0 <= lane <= 1.
+ // fp16 is the only variant for which these two differ.
+ // https://developer.arm.com/documentation/ihi0073/latest/
+ defvar getlanety = !if(!eq(type, "h"), lanety, laneqty);
def : SOpInst<"vcmla" # ROT # "_laneq", "...QI", type, Op<(call "vcmla"
# ROT, $p0, $p1,
- (bitcast $p0, (dup_typed lanety, (call "vget_lane", (bitcast
laneqty, $p2), $p3))))>>;
-
+ (bitcast $p0, (dup_typed lanety, (call "vget_lane", (bitcast
getlanety, $p2), $p3))))>>;
----------------
Lukacma wrote:
Apologies got confused there. Now I see what you are talking about. But to me
it seems that whoever wrote this part of ACLE still wanted to allow lane to be
from 0 to 3 and got around this limitation of the instruction by using DUP . So
if we want to be consistent with ACLE we should still allow this wider range.
Or do you think we should go and propose changing ACLE for this variant?
https://github.com/llvm/llvm-project/pull/100278
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