================
@@ -59,16 +59,26 @@ let TargetPrefix = "riscv" in {
[IntrNoMem, IntrWillReturn, IntrSpeculatable,
ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
+ def int_riscv_cv_alu_slet : ScalarCoreVAluGprGprIntrinsic;
----------------
jeremybennett wrote:
> I also note that conversations like this is why standard RISC-V builtins go
> through a review process seen by developers of both toolchains. I would
> encourage CORE-V to do the same if they don't want to be surprised by
> pushback for things that developers of certain toolchains think don't make
> sense.
@jrtc27 We have to put our hands up on this one. For a long time the CORE-V
and its ancestors have only had GCC tool chains, so the engagement was with
that community. The LLVM implementation is newer, but we should have reached
out early in the project.
How would you suggest we progress given where we are?
https://github.com/llvm/llvm-project/pull/100684
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