================
@@ -1959,9 +2064,12 @@ multiclass VCMLA_ROTS<string type, string lanety, string
laneqty> {
let isLaneQ = 1 in {
// vcmla{ROT}_laneq
+ // ACLE specifies that the fp16 vcmla_#ROT_laneq variant has an
immedaite range of 0 <= lane <= 1.
+ // fp16 is the only variant for which these two differ.
+ // https://developer.arm.com/documentation/ihi0073/latest/
+ defvar getlanety = !if(!eq(type, "h"), lanety, laneqty);
def : SOpInst<"vcmla" # ROT # "_laneq", "...QI", type, Op<(call "vcmla"
# ROT, $p0, $p1,
- (bitcast $p0, (dup_typed lanety, (call "vget_lane", (bitcast
laneqty, $p2), $p3))))>>;
-
+ (bitcast $p0, (dup_typed lanety, (call "vget_lane", (bitcast
getlanety, $p2), $p3))))>>;
----------------
Lukacma wrote:
I did take a look into [ACLE
release](https://github.com/ARM-software/acle/releases/tag/r2024Q2) and I think
the website you linked might have a mistake there. Looking at advsimd-2023Q2 I
see `vcmla[_rot]_laneq_f16` defined like this :
<img width="725" alt="image"
src="https://github.com/user-attachments/assets/2a446a5c-a3bf-40fc-9950-6caee95d81a2";>
It also makes sense for all of them to have the same imm. range, as the range
is only dependant on size and datatype of the 3 operand and not on the sizes
and datatypes of the other operands.
https://github.com/llvm/llvm-project/pull/100278
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