[clang] [llvm] [RISCV] Implement Clang Builtins for XCValu Extension in CV32E40P (PR #100684)

[Craig Topper via cfe-commits]

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@@ -59,16 +59,26 @@ let TargetPrefix = "riscv" in {
                             [IntrNoMem, IntrWillReturn, IntrSpeculatable,
                             ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
 
+  def int_riscv_cv_alu_slet  : ScalarCoreVAluGprGprIntrinsic;
+  def int_riscv_cv_alu_sletu : ScalarCoreVAluGprGprIntrinsic;
+  def int_riscv_cv_alu_min   : ScalarCoreVAluGprGprIntrinsic;
+  def int_riscv_cv_alu_minu  : ScalarCoreVAluGprGprIntrinsic;
+  def int_riscv_cv_alu_max   : ScalarCoreVAluGprGprIntrinsic;
+  def int_riscv_cv_alu_maxu  : ScalarCoreVAluGprGprIntrinsic;
+  def int_riscv_cv_alu_exths : ScalarCoreVAluGprIntrinsic;
----------------
topperc wrote:

The extends can be directly expressed in IR with shifts or truncate+extend. I 
don't think we need intrinsics.

https://github.com/llvm/llvm-project/pull/100684
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