https://github.com/jyknight updated
https://github.com/llvm/llvm-project/pull/98273
>From 546963316017935bfbbc05d7095d645344fbd5f5 Mon Sep 17 00:00:00 2001
From: James Y Knight <jykni...@google.com>
Date: Wed, 10 Jul 2024 00:49:25 -0400
Subject: [PATCH 1/3] Clang: don't unnecessarily convert inline-asm operands to
x86mmx in IR.
The SelectionDAG asm-lowering code can already handle conversion of other
vector types to MMX if needed.
---
clang/lib/CodeGen/Targets/X86.cpp | 13 -------------
clang/test/CodeGen/X86/mmx-inline-asm.c | 2 +-
clang/test/CodeGen/asm-inout.c | 6 +++---
llvm/lib/Target/X86/X86ISelLowering.cpp | 6 +++---
llvm/test/CodeGen/X86/mmx-inlineasm.ll | 20 ++++++++++++++++++++
5 files changed, 27 insertions(+), 20 deletions(-)
create mode 100644 llvm/test/CodeGen/X86/mmx-inlineasm.ll
diff --git a/clang/lib/CodeGen/Targets/X86.cpp
b/clang/lib/CodeGen/Targets/X86.cpp
index 3146caba1c615..7fb9a4c070873 100644
--- a/clang/lib/CodeGen/Targets/X86.cpp
+++ b/clang/lib/CodeGen/Targets/X86.cpp
@@ -27,19 +27,6 @@ bool IsX86_MMXType(llvm::Type *IRType) {
static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
StringRef Constraint,
llvm::Type* Ty) {
- bool IsMMXCons = llvm::StringSwitch<bool>(Constraint)
- .Cases("y", "&y", "^Ym", true)
- .Default(false);
- if (IsMMXCons && Ty->isVectorTy()) {
- if (cast<llvm::VectorType>(Ty)->getPrimitiveSizeInBits().getFixedValue() !=
- 64) {
- // Invalid MMX constraint
- return nullptr;
- }
-
- return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
- }
-
if (Constraint == "k") {
llvm::Type *Int1Ty = llvm::Type::getInt1Ty(CGF.getLLVMContext());
return llvm::FixedVectorType::get(Int1Ty, Ty->getScalarSizeInBits());
diff --git a/clang/test/CodeGen/X86/mmx-inline-asm.c
b/clang/test/CodeGen/X86/mmx-inline-asm.c
index 19c24a3a91e14..a0702c7f780d1 100644
--- a/clang/test/CodeGen/X86/mmx-inline-asm.c
+++ b/clang/test/CodeGen/X86/mmx-inline-asm.c
@@ -1,7 +1,7 @@
// RUN: %clang_cc1 -emit-llvm -triple i386 -target-feature +mmx %s -o - |
FileCheck %s
#include <mmintrin.h>
-// CHECK: { x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx }
+// CHECK: { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>,
<1 x i64> }
void foo(long long fill) {
__m64 vfill = _mm_cvtsi64_m64(fill);
diff --git a/clang/test/CodeGen/asm-inout.c b/clang/test/CodeGen/asm-inout.c
index 1383a421efbc2..6d40451b778d9 100644
--- a/clang/test/CodeGen/asm-inout.c
+++ b/clang/test/CodeGen/asm-inout.c
@@ -38,11 +38,11 @@ int test4(volatile int *addr) {
return (int)oldval;
}
-// This should have both inputs be of type x86_mmx.
+// This should have both inputs be of type <1 x i64>.
// CHECK: @test5
typedef long long __m64 __attribute__((__vector_size__(8)));
__m64 test5(__m64 __A, __m64 __B) {
- // CHECK: call x86_mmx asm "pmulhuw $1, $0\0A\09",
"=y,y,0,~{dirflag},~{fpsr},~{flags}"(x86_mmx %{{.*}}, x86_mmx %{{.*}})
+ // CHECK: call <1 x i64> asm "pmulhuw $1, $0\0A\09",
"=y,y,0,~{dirflag},~{fpsr},~{flags}"(<1 x i64> %{{.*}}, <1 x i64> %{{.*}})
asm ("pmulhuw %1, %0\n\t" : "+y" (__A) : "y" (__B));
return __A;
}
@@ -51,7 +51,7 @@ __m64 test5(__m64 __A, __m64 __B) {
int test6(void) {
typedef unsigned char __attribute__((vector_size(8))) _m64u8;
_m64u8 __attribute__((aligned(16))) Mu8_0, __attribute__((aligned(16)))
Mu8_1;
- // CHECK: call x86_mmx asm "nop", "=y,0,~{dirflag},~{fpsr},~{flags}"(x86_mmx
%1)
+ // CHECK: call <8 x i8> asm "nop", "=y,0,~{dirflag},~{fpsr},~{flags}"(<8 x
i8> %0)
asm ("nop" : "=y"(Mu8_1 ) : "0"(Mu8_0 ));
return 0;
}
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 50cacc3038b0c..d2e7074c59077 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -58150,7 +58150,7 @@ X86TargetLowering::getSingleConstraintMatchWeight(
Wt = CW_SpecificReg;
break;
case 'y':
- if (Ty->isX86_MMXTy() && Subtarget.hasMMX())
+ if (Ty->getPrimitiveSizeInBits() == 64 && Subtarget.hasMMX())
Wt = CW_SpecificReg;
break;
case 'Y':
@@ -58173,8 +58173,8 @@ X86TargetLowering::getSingleConstraintMatchWeight(
return CW_Invalid;
// Any MMX reg
case 'm':
- if (Ty->isX86_MMXTy() && Subtarget.hasMMX())
- return Wt;
+ if (Ty->getPrimitiveSizeInBits() == 64 && Subtarget.hasMMX())
+ return CW_SpecificReg;
return CW_Invalid;
// Any SSE reg when ISA >= SSE2, same as 'x'
case 'i':
diff --git a/llvm/test/CodeGen/X86/mmx-inlineasm.ll
b/llvm/test/CodeGen/X86/mmx-inlineasm.ll
new file mode 100644
index 0000000000000..5a15600a4b312
--- /dev/null
+++ b/llvm/test/CodeGen/X86/mmx-inlineasm.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx | FileCheck %s
+
+;; Verify that the mmx 'y' constraint works with arbitrary IR types.
+define <2 x i32> @test_mmx_asm(<2 x i32> %a) nounwind {
+; CHECK-LABEL: test_mmx_asm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movdq2q %xmm0, %mm0
+; CHECK-NEXT: #APP
+; CHECK-NEXT: # %mm0 = %mm0
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: #APP
+; CHECK-NEXT: # %mm0 = %mm0
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: movq2dq %mm0, %xmm0
+; CHECK-NEXT: retq
+ %1 = tail call i64 asm sideeffect "# $0 = $1", "=y,y"(<2 x i32> %a)
+ %2 = tail call <2 x i32> asm sideeffect "# $0 = $1", "=y,y"(i64 %1)
+ ret <2 x i32> %2
+}
>From aa61b20682ff1066a1c7d6b1241f051710a1a6ed Mon Sep 17 00:00:00 2001
From: James Y Knight <jykni...@google.com>
Date: Thu, 11 Jul 2024 14:51:26 -0400
Subject: [PATCH 2/3] fix clang-format
---
clang/lib/CodeGen/Targets/X86.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/clang/lib/CodeGen/Targets/X86.cpp
b/clang/lib/CodeGen/Targets/X86.cpp
index 7fb9a4c070873..5d33a8f5f36c9 100644
--- a/clang/lib/CodeGen/Targets/X86.cpp
+++ b/clang/lib/CodeGen/Targets/X86.cpp
@@ -24,9 +24,9 @@ bool IsX86_MMXType(llvm::Type *IRType) {
IRType->getScalarSizeInBits() != 64;
}
-static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
+static llvm::Type *X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
StringRef Constraint,
- llvm::Type* Ty) {
+ llvm::Type *Ty) {
if (Constraint == "k") {
llvm::Type *Int1Ty = llvm::Type::getInt1Ty(CGF.getLLVMContext());
return llvm::FixedVectorType::get(Int1Ty, Ty->getScalarSizeInBits());
>From 0798768bbada423ab4e169294daa64ff71d5ed5a Mon Sep 17 00:00:00 2001
From: James Y Knight <jykni...@google.com>
Date: Tue, 23 Jul 2024 13:14:41 -0400
Subject: [PATCH 3/3] Add Ym test.
---
llvm/test/CodeGen/X86/mmx-inlineasm.ll | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/llvm/test/CodeGen/X86/mmx-inlineasm.ll
b/llvm/test/CodeGen/X86/mmx-inlineasm.ll
index 5a15600a4b312..86fca9051dab4 100644
--- a/llvm/test/CodeGen/X86/mmx-inlineasm.ll
+++ b/llvm/test/CodeGen/X86/mmx-inlineasm.ll
@@ -18,3 +18,21 @@ define <2 x i32> @test_mmx_asm(<2 x i32> %a) nounwind {
%2 = tail call <2 x i32> asm sideeffect "# $0 = $1", "=y,y"(i64 %1)
ret <2 x i32> %2
}
+
+;; And same thing with the 'Ym' constraint.
+define <2 x i32> @test_mmx_asm_Ym(<2 x i32> %a) nounwind {
+; CHECK-LABEL: test_mmx_asm_Ym:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movdq2q %xmm0, %mm0
+; CHECK-NEXT: #APP
+; CHECK-NEXT: # %mm0 = %mm0
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: #APP
+; CHECK-NEXT: # %mm0 = %mm0
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: movq2dq %mm0, %xmm0
+; CHECK-NEXT: retq
+ %1 = tail call i64 asm sideeffect "# $0 = $1", "=^Ym,^Ym"(<2 x i32> %a)
+ %2 = tail call <2 x i32> asm sideeffect "# $0 = $1", "=^Ym,^Ym"(i64 %1)
+ ret <2 x i32> %2
+}
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