Author: Jianjian Guan Date: 2024-06-21T11:11:10+08:00 New Revision: 762546565173e27b1851dfd1f3bfcc7fc847a2f9
URL: https://github.com/llvm/llvm-project/commit/762546565173e27b1851dfd1f3bfcc7fc847a2f9 DIFF: https://github.com/llvm/llvm-project/commit/762546565173e27b1851dfd1f3bfcc7fc847a2f9.diff LOG: [RISCV] Make M imply Zmmul (#95070) According to the spec, M implies Zmmul. Added: Modified: clang/lib/Basic/Targets/RISCV.cpp clang/test/CodeGen/RISCV/riscv-func-attr-target.c lld/test/ELF/lto/riscv-attributes.ll lld/test/ELF/riscv-attributes.s llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp llvm/lib/Target/RISCV/RISCVFeatures.td llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVInstrInfo.cpp llvm/lib/Target/RISCV/RISCVInstrInfoM.td llvm/lib/Target/RISCV/RISCVInstrInfoZc.td llvm/test/CodeGen/RISCV/attributes-module-flag.ll llvm/test/CodeGen/RISCV/attributes.ll llvm/test/MC/RISCV/attribute-arch.s llvm/test/MC/RISCV/attribute.s llvm/test/MC/RISCV/default-build-attributes.s llvm/test/MC/RISCV/rv32zcb-valid.s llvm/unittests/TargetParser/RISCVISAInfoTest.cpp Removed: ################################################################################ diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index a7ce9dda34bdd..25ae7d64b577e 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -168,7 +168,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts, Twine(getVersionValue(ExtInfo.Major, ExtInfo.Minor))); } - if (ISAInfo->hasExtension("m") || ISAInfo->hasExtension("zmmul")) + if (ISAInfo->hasExtension("zmmul")) Builder.defineMacro("__riscv_mul"); if (ISAInfo->hasExtension("m")) { diff --git a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c index 1f8682179ea81..aeddbc4ebf689 100644 --- a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c +++ b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c @@ -66,16 +66,16 @@ void test_rvv_f64_type_w_zve64d() { } //. -// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei,-relax,-zbb,-zfa" } -// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" } -// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa" } -// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zbb,+zicond,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" } +// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei,+zmmul,-relax,-zbb,-zfa" } +// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" } +// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,+zmmul,-relax,-zfa" } +// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zbb,+zicond,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" } // Make sure we append negative features if we override the arch -// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" } -// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" } -// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa" } -// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+m,+save-restore,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" } -// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" } -// CHECK: attributes #9 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zicsr,+zifencei,+zve32x,+zvl32b,-relax,-zbb,-zfa" } -// CHECK: attributes #11 = { {{.*}}"target-features"="+64bit,+a,+f,+m,+save-restore,+zicsr,+zifencei,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa" } -// CHECK: attributes #12 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b,-relax,-zbb,-zfa" } +// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" } +// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" } +// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,+zmmul,-relax,-zfa" } +// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" } +// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" } +// CHECK: attributes #9 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32x,+zvl32b,-relax,-zbb,-zfa" } +// CHECK: attributes #11 = { {{.*}}"target-features"="+64bit,+a,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa" } +// CHECK: attributes #12 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b,-relax,-zbb,-zfa" } diff --git a/lld/test/ELF/lto/riscv-attributes.ll b/lld/test/ELF/lto/riscv-attributes.ll index 802eac0bc5106..08d8ad43dd71e 100644 --- a/lld/test/ELF/lto/riscv-attributes.ll +++ b/lld/test/ELF/lto/riscv-attributes.ll @@ -10,10 +10,10 @@ ; CHECK: BuildAttributes { ; CHECK-NEXT: FormatVersion: 0x41 ; CHECK-NEXT: Section 1 { -; CHECK-NEXT: SectionLength: 70 +; CHECK-NEXT: SectionLength: 79 ; CHECK-NEXT: Vendor: riscv ; CHECK-NEXT: Tag: Tag_File (0x1) -; CHECK-NEXT: Size: 60 +; CHECK-NEXT: Size: 69 ; CHECK-NEXT: FileAttributes { ; CHECK-NEXT: Attribute { ; CHECK-NEXT: Tag: 4 @@ -30,7 +30,7 @@ ; CHECK-NEXT: Attribute { ; CHECK-NEXT: Tag: 5 ; CHECK-NEXT: TagName: arch -; CHECK-NEXT: Value: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zbb1p0{{$}} +; CHECK-NEXT: Value: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zbb1p0{{$}} ; CHECK-NEXT: } ; CHECK-NEXT: } ; CHECK-NEXT: } @@ -38,10 +38,10 @@ ;--- 1.s .attribute 4, 16 -.attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0" +.attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zmmul1p0" ;--- 2.s .attribute 4, 16 -.attribute 5, "rv32i2p1_m2p0_f2p2_d2p2_zbb1p0" +.attribute 5, "rv32i2p1_m2p0_f2p2_d2p2_zbb1p0_zmmul1p0" .attribute 6, 1 ;--- a.ll diff --git a/lld/test/ELF/riscv-attributes.s b/lld/test/ELF/riscv-attributes.s index d0ce0941269ec..68534d0fb6b75 100644 --- a/lld/test/ELF/riscv-attributes.s +++ b/lld/test/ELF/riscv-attributes.s @@ -64,20 +64,20 @@ # UNKNOWN22: warning: unknown22a.o:(.riscv.attributes): invalid tag 0x16 at offset 0x10 # HDR: Name Type Address Off Size ES Flg Lk Inf Al -# HDR: .riscv.attributes RISCV_ATTRIBUTES 0000000000000000 000158 00003e 00 0 0 1{{$}} +# HDR: .riscv.attributes RISCV_ATTRIBUTES 0000000000000000 000158 000047 00 0 0 1{{$}} # HDR: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align # HDR: LOAD 0x000000 0x0000000000010000 0x0000000000010000 0x000158 0x000158 R 0x1000 # HDR-NEXT: GNU_STACK 0x000000 0x0000000000000000 0x0000000000000000 0x000000 0x000000 RW 0 -# HDR-NEXT: ATTRIBUTES 0x000158 0x0000000000000000 0x0000000000000000 0x00003e 0x00003e R 0x1{{$}} +# HDR-NEXT: ATTRIBUTES 0x000158 0x0000000000000000 0x0000000000000000 0x000047 0x000047 R 0x1{{$}} # CHECK: BuildAttributes { # CHECK-NEXT: FormatVersion: 0x41 # CHECK-NEXT: Section 1 { -# CHECK-NEXT: SectionLength: 61 +# CHECK-NEXT: SectionLength: 70 # CHECK-NEXT: Vendor: riscv # CHECK-NEXT: Tag: Tag_File (0x1) -# CHECK-NEXT: Size: 51 +# CHECK-NEXT: Size: 60 # CHECK-NEXT: FileAttributes { # CHECK-NEXT: Attribute { # CHECK-NEXT: Tag: 4 @@ -88,7 +88,7 @@ # CHECK-NEXT: Attribute { # CHECK-NEXT: Tag: 5 # CHECK-NEXT: TagName: arch -# CHECK-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0{{$}} +# CHECK-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0{{$}} # CHECK-NEXT: } # CHECK-NEXT: } # CHECK-NEXT: } @@ -97,10 +97,10 @@ # CHECK2: BuildAttributes { # CHECK2-NEXT: FormatVersion: 0x41 # CHECK2-NEXT: Section 1 { -# CHECK2-NEXT: SectionLength: 104 +# CHECK2-NEXT: SectionLength: 113 # CHECK2-NEXT: Vendor: riscv # CHECK2-NEXT: Tag: Tag_File (0x1) -# CHECK2-NEXT: Size: 94 +# CHECK2-NEXT: Size: 103 # CHECK2-NEXT: FileAttributes { # CHECK2-NEXT: Attribute { # CHECK2-NEXT: Tag: 4 @@ -127,7 +127,7 @@ # CHECK2-NEXT: Attribute { # CHECK2-NEXT: Tag: 5 # CHECK2-NEXT: TagName: arch -# CHECK2-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0{{$}} +# CHECK2-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0{{$}} # CHECK2-NEXT: } # CHECK2-NEXT: } # CHECK2-NEXT: } @@ -152,12 +152,12 @@ #--- a.s .attribute stack_align, 16 -.attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0" +.attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zmmul1p0" .attribute unaligned_access, 0 #--- b.s .attribute stack_align, 16 -.attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0" +.attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zmmul1p0" .attribute priv_spec, 2 .attribute priv_spec_minor, 2 diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp index 7cd10d785d820..e003b6b8ee4e1 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp @@ -305,7 +305,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) getActionDefinitionsBuilder({G_GLOBAL_VALUE, G_JUMP_TABLE, G_CONSTANT_POOL}) .legalFor({p0}); - if (ST.hasStdExtM() || ST.hasStdExtZmmul()) { + if (ST.hasStdExtZmmul()) { getActionDefinitionsBuilder(G_MUL) .legalFor({s32, sXLen}) .widenScalarToNextPow2(0) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index d313405c01761..a5e34def81c85 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -171,23 +171,21 @@ def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">; // Multiply Extensions +def FeatureStdExtZmmul + : RISCVExtension<"zmmul", 1, 0, + "'Zmmul' (Integer Multiplication)">; +def HasStdExtZmmul : Predicate<"Subtarget->hasStdExtZmmul()">, + AssemblerPredicate<(all_of FeatureStdExtZmmul), + "'Zmmul' (Integer Multiplication)">; + def FeatureStdExtM : RISCVExtension<"m", 2, 0, - "'M' (Integer Multiplication and Division)">; + "'M' (Integer Multiplication and Division)", + [FeatureStdExtZmmul]>; def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, AssemblerPredicate<(all_of FeatureStdExtM), "'M' (Integer Multiplication and Division)">; -def FeatureStdExtZmmul - : RISCVExtension<"zmmul", 1, 0, - "'Zmmul' (Integer Multiplication)">; - -def HasStdExtMOrZmmul - : Predicate<"Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul()">, - AssemblerPredicate<(any_of FeatureStdExtM, FeatureStdExtZmmul), - "'M' (Integer Multiplication and Division) or " - "'Zmmul' (Integer Multiplication)">; - // Atomic Extensions def FeatureStdExtA diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 57817832c9b42..a02fd5bd1b65e 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -300,7 +300,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setLibcallName(RTLIB::MULO_I64, nullptr); } - if (!Subtarget.hasStdExtM() && !Subtarget.hasStdExtZmmul()) { + if (!Subtarget.hasStdExtZmmul()) { setOperationAction({ISD::MUL, ISD::MULHS, ISD::MULHU}, XLenVT, Expand); if (RV64LegalI32 && Subtarget.is64Bit()) setOperationAction(ISD::MUL, MVT::i32, Promote); @@ -21144,14 +21144,13 @@ bool RISCVTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) bool RISCVTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const { // Check integral scalar types. - const bool HasExtMOrZmmul = - Subtarget.hasStdExtM() || Subtarget.hasStdExtZmmul(); + const bool HasZmmul = Subtarget.hasStdExtZmmul(); if (!VT.isScalarInteger()) return false; // Omit the optimization if the sub target has the M extension and the data // size exceeds XLen. - if (HasExtMOrZmmul && VT.getSizeInBits() > Subtarget.getXLen()) + if (HasZmmul && VT.getSizeInBits() > Subtarget.getXLen()) return false; if (auto *ConstNode = dyn_cast<ConstantSDNode>(C.getNode())) { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 444b9076005c2..00eb83da652b7 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -3695,7 +3695,7 @@ void RISCVInstrInfo::mulImm(MachineFunction &MF, MachineBasicBlock &MBB, .addReg(ScaledRegister, RegState::Kill) .addReg(DestReg, RegState::Kill) .setMIFlag(Flag); - } else if (STI.hasStdExtM() || STI.hasStdExtZmmul()) { + } else if (STI.hasStdExtZmmul()) { Register N = MRI.createVirtualRegister(&RISCV::GPRRegClass); movImm(MBB, II, DL, N, Amount, Flag); BuildMI(MBB, II, DL, get(RISCV::MUL), DestReg) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoM.td b/llvm/lib/Target/RISCV/RISCVInstrInfoM.td index 8ea1560e5b372..8a2b32081dc5f 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoM.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoM.td @@ -24,7 +24,7 @@ def riscv_remuw : SDNode<"RISCVISD::REMUW", SDT_RISCVIntBinOpW>; // Instructions //===----------------------------------------------------------------------===// -let Predicates = [HasStdExtMOrZmmul] in { +let Predicates = [HasStdExtZmmul] in { def MUL : ALU_rr<0b0000001, 0b000, "mul", Commutable=1>, Sched<[WriteIMul, ReadIMul, ReadIMul]>; def MULH : ALU_rr<0b0000001, 0b001, "mulh", Commutable=1>, @@ -33,7 +33,7 @@ def MULHSU : ALU_rr<0b0000001, 0b010, "mulhsu">, Sched<[WriteIMul, ReadIMul, ReadIMul]>; def MULHU : ALU_rr<0b0000001, 0b011, "mulhu", Commutable=1>, Sched<[WriteIMul, ReadIMul, ReadIMul]>; -} // Predicates = [HasStdExtMOrZmmul] +} // Predicates = [HasStdExtZmmul] let Predicates = [HasStdExtM] in { def DIV : ALU_rr<0b0000001, 0b100, "div">, @@ -46,10 +46,10 @@ def REMU : ALU_rr<0b0000001, 0b111, "remu">, Sched<[WriteIRem, ReadIRem, ReadIRem]>; } // Predicates = [HasStdExtM] -let Predicates = [HasStdExtMOrZmmul, IsRV64], IsSignExtendingOpW = 1 in { +let Predicates = [HasStdExtZmmul, IsRV64], IsSignExtendingOpW = 1 in { def MULW : ALUW_rr<0b0000001, 0b000, "mulw", Commutable=1>, Sched<[WriteIMul32, ReadIMul32, ReadIMul32]>; -} // Predicates = [HasStdExtMOrZmmul, IsRV64] +} // Predicates = [HasStdExtZmmul, IsRV64] let Predicates = [HasStdExtM, IsRV64], IsSignExtendingOpW = 1 in { def DIVW : ALUW_rr<0b0000001, 0b100, "divw">, @@ -66,12 +66,12 @@ def REMUW : ALUW_rr<0b0000001, 0b111, "remuw">, // Pseudo-instructions and codegen patterns //===----------------------------------------------------------------------===// -let Predicates = [HasStdExtMOrZmmul] in { +let Predicates = [HasStdExtZmmul] in { def : PatGprGpr<mul, MUL>; def : PatGprGpr<mulhs, MULH>; def : PatGprGpr<mulhu, MULHU>; def : PatGprGpr<riscv_mulhsu, MULHSU>; -} // Predicates = [HasStdExtMOrZmmul] +} // Predicates = [HasStdExtZmmul] let Predicates = [HasStdExtM] in { def : PatGprGpr<sdiv, DIV>; @@ -81,7 +81,7 @@ def : PatGprGpr<urem, REMU>; } // Predicates = [HasStdExtM] // Select W instructions if only the lower 32-bits of the result are used. -let Predicates = [HasStdExtMOrZmmul, IsRV64] in +let Predicates = [HasStdExtZmmul, IsRV64] in def : PatGprGpr<binop_allwusers<mul>, MULW>; let Predicates = [HasStdExtM, IsRV64] in { @@ -106,20 +106,20 @@ def : Pat<(srem (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR:$rs2))), (REMW GPR:$rs1, GPR:$rs2)>; } // Predicates = [HasStdExtM, IsRV64] -let Predicates = [HasStdExtMOrZmmul, IsRV64, NotHasStdExtZba] in { +let Predicates = [HasStdExtZmmul, IsRV64, NotHasStdExtZba] in { // Special case for calculating the full 64-bit product of a 32x32 unsigned // multiply where the inputs aren't known to be zero extended. We can shift the // inputs left by 32 and use a MULHU. This saves two SRLIs needed to finish // zeroing the upper 32 bits. def : Pat<(i64 (mul (and GPR:$rs1, 0xffffffff), (and GPR:$rs2, 0xffffffff))), (MULHU (i64 (SLLI GPR:$rs1, 32)), (i64 (SLLI GPR:$rs2, 32)))>; -} // Predicates = [HasStdExtMOrZmmul, IsRV64, NotHasStdExtZba] +} // Predicates = [HasStdExtZmmul, IsRV64, NotHasStdExtZba] //===----------------------------------------------------------------------===// // Experimental RV64 i32 legalization patterns. //===----------------------------------------------------------------------===// -let Predicates = [HasStdExtMOrZmmul, IsRV64] in { +let Predicates = [HasStdExtZmmul, IsRV64] in { def : PatGprGpr<mul, MULW, i32, i32>; } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td index 2a4448d7881fb..11c2695a59854 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td @@ -183,7 +183,7 @@ let Predicates = [HasStdExtZcb] in def C_ZEXT_B : RVZcArith_r<0b11000 , "c.zext.b">, Sched<[WriteIALU, ReadIALU]>; -let Predicates = [HasStdExtZcb, HasStdExtMOrZmmul] in +let Predicates = [HasStdExtZcb, HasStdExtZmmul] in def C_MUL : CA_ALU<0b100111, 0b10, "c.mul", GPRC>, Sched<[WriteIMul, ReadIMul, ReadIMul]>; @@ -270,13 +270,13 @@ def CM_JALT : RVInst16CJ<0b101, 0b10, (outs), (ins uimm8ge32:$index), } // DecoderNamespace = "RVZcmt", Predicates = [HasStdExtZcmt]... -let Predicates = [HasStdExtZcb, HasStdExtMOrZmmul] in{ +let Predicates = [HasStdExtZcb, HasStdExtZmmul] in{ def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs1, GPRC:$rs2), (C_MUL GPRC:$rs1, GPRC:$rs2)>; let isCompressOnly = true in def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs2, GPRC:$rs1), (C_MUL GPRC:$rs1, GPRC:$rs2)>; -} // Predicates = [HasStdExtZcb, HasStdExtMOrZmmul] +} // Predicates = [HasStdExtZcb, HasStdExtZmmul] let Predicates = [HasStdExtZcb, HasStdExtZbb] in{ def : CompressPat<(SEXT_B GPRC:$rs1, GPRC:$rs1), diff --git a/llvm/test/CodeGen/RISCV/attributes-module-flag.ll b/llvm/test/CodeGen/RISCV/attributes-module-flag.ll index 4580539fbb29b..2b553c03aceee 100644 --- a/llvm/test/CodeGen/RISCV/attributes-module-flag.ll +++ b/llvm/test/CodeGen/RISCV/attributes-module-flag.ll @@ -3,8 +3,8 @@ ; Test generation of ELF attribute from module metadata -; RV32: .attribute 5, "rv32i2p1_m2p0_zba1p0" -; RV64: .attribute 5, "rv64i2p1_m2p0_zba1p0" +; RV32: .attribute 5, "rv32i2p1_m2p0_zmmul1p0_zba1p0" +; RV64: .attribute 5, "rv64i2p1_m2p0_zmmul1p0_zba1p0" define i32 @addi(i32 %a) { %1 = add i32 %a, 1 diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 539f0e1a67947..f20f6f7c6f94e 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -283,7 +283,7 @@ ; CHECK: .attribute 4, 16 -; RV32M: .attribute 5, "rv32i2p1_m2p0" +; RV32M: .attribute 5, "rv32i2p1_m2p0_zmmul1p0" ; RV32ZMMUL: .attribute 5, "rv32i2p1_zmmul1p0" ; RV32MZMMUL: .attribute 5, "rv32i2p1_m2p0_zmmul1p0" ; RV32A: .attribute 5, "rv32i2p1_a2p1" @@ -413,7 +413,7 @@ ; RV32SUPM: .attribute 5, "rv32i2p1_supm0p8" ; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0" -; RV64M: .attribute 5, "rv64i2p1_m2p0" +; RV64M: .attribute 5, "rv64i2p1_m2p0_zmmul1p0" ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0" ; RV64MZMMUL: .attribute 5, "rv64i2p1_m2p0_zmmul1p0" ; RV64A: .attribute 5, "rv64i2p1_a2p1" @@ -551,15 +551,15 @@ ; RVI20U32: .attribute 5, "rv32i2p1" ; RVI20U64: .attribute 5, "rv64i2p1" -; RVA20U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_za128rs1p0" -; RVA20S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_za128rs1p0_ssccptr1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0" -; RVA22U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zihintpause2p0_zihpm2p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" -; RVA22S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscounterenw1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svpbmt1p0" -; RVA23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" -; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm0p8_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" -; RVB23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" -; RVB23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" -; RVM23U32: .attribute 5, "rv32i2p1_m2p0_zicbop1p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zimop1p0_zca1p0_zcb1p0_zce1p0_zcmop1p0_zcmp1p0_zcmt1p0_zba1p0_zbb1p0_zbs1p0" +; RVA20U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zmmul1p0_za128rs1p0" +; RVA20S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zmmul1p0_za128rs1p0_ssccptr1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0" +; RVA22U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" +; RVA22S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscounterenw1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svpbmt1p0" +; RVA23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" +; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm0p8_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" +; RVB23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" +; RVB23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" +; RVM23U32: .attribute 5, "rv32i2p1_m2p0_zicbop1p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zimop1p0_zmmul1p0_zca1p0_zcb1p0_zce1p0_zcmop1p0_zcmp1p0_zcmt1p0_zba1p0_zbb1p0_zbs1p0" define i32 @addi(i32 %a) { %1 = add i32 %a, 1 diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 6e48a742d8d7d..e8029ba71cb69 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -17,25 +17,25 @@ # CHECK-RV64: attribute 5, "rv64e2p0" .attribute arch, "rv32i2p1_m2" -# CHECK: attribute 5, "rv32i2p1_m2p0" +# CHECK: attribute 5, "rv32i2p1_m2p0_zmmul1p0" .attribute arch, "rv32i2p1_ma" -# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1" +# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_zmmul1p0" .attribute arch, "rv32g" -# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0" +# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0" .attribute arch, "rv32imafdc" -# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0" +# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0" .attribute arch, "rv32i2p1_mafdc" -# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0" +# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0" .attribute arch, "rv32ima2p1_fdc" -# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0" +# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0" .attribute arch, "rv32ima2p1_fdc" -# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0" +# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0" .attribute arch, "rv32iv" # CHECK: attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" diff --git a/llvm/test/MC/RISCV/attribute.s b/llvm/test/MC/RISCV/attribute.s index 56f0cb1daf176..7685df46eb723 100644 --- a/llvm/test/MC/RISCV/attribute.s +++ b/llvm/test/MC/RISCV/attribute.s @@ -10,8 +10,8 @@ .attribute stack_align, 16 # CHECK: attribute 4, 16 -.attribute arch, "rv32i2p1_m2p0_a2p1_c2p0" -# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_c2p0" +.attribute arch, "rv32i2p1_m2p0_a2p1_c2p0_zmmul1p0" +# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_c2p0_zmmul1p0" .attribute unaligned_access, 0 # CHECK: attribute 6, 0 diff --git a/llvm/test/MC/RISCV/default-build-attributes.s b/llvm/test/MC/RISCV/default-build-attributes.s index 3f96ca0a46c42..7d34957172ad6 100644 --- a/llvm/test/MC/RISCV/default-build-attributes.s +++ b/llvm/test/MC/RISCV/default-build-attributes.s @@ -14,7 +14,7 @@ # RV64: attribute 5, "rv64i2p1" # RV32M-NOT: attribute 4 -# RV32M: attribute 5, "rv32i2p1_m2p0" +# RV32M: attribute 5, "rv32i2p1_m2p0_zmmul1p0" # RV64M-NOT: attribute 4 -# RV64M: attribute 5, "rv64i2p1_m2p0" +# RV64M: attribute 5, "rv64i2p1_m2p0_zmmul1p0" diff --git a/llvm/test/MC/RISCV/rv32zcb-valid.s b/llvm/test/MC/RISCV/rv32zcb-valid.s index d3ff23dbc2f8f..de25a389b995c 100644 --- a/llvm/test/MC/RISCV/rv32zcb-valid.s +++ b/llvm/test/MC/RISCV/rv32zcb-valid.s @@ -43,7 +43,7 @@ c.not s0 # CHECK-ASM-AND-OBJ: c.mul s0, s1 # CHECK-ASM: encoding: [0x45,0x9c] -# CHECK-NO-EXT: error: instruction requires the following: 'M' (Integer Multiplication and Division) or 'Zmmul' (Integer Multiplication), 'Zcb' (Compressed basic bit manipulation instructions){{$}} +# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Compressed basic bit manipulation instructions), 'Zmmul' (Integer Multiplication) c.mul s0, s1 # CHECK-ASM-AND-OBJ: c.lbu a5, 2(a4) diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 7d46aae882640..60bbf01c6276b 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -223,7 +223,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { ASSERT_THAT_EXPECTED(MaybeRV32G, Succeeded()); RISCVISAInfo &InfoRV32G = **MaybeRV32G; const auto &ExtsRV32G = InfoRV32G.getExtensions(); - EXPECT_EQ(ExtsRV32G.size(), 7UL); + EXPECT_EQ(ExtsRV32G.size(), 8UL); EXPECT_TRUE(ExtsRV32G.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1})); EXPECT_TRUE(ExtsRV32G.at("m") == (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_TRUE(ExtsRV32G.at("a") == (RISCVISAUtils::ExtensionVersion{2, 1})); @@ -232,6 +232,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { EXPECT_TRUE(ExtsRV32G.at("zicsr") == (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_TRUE(ExtsRV32G.at("zifencei") == (RISCVISAUtils::ExtensionVersion{2, 0})); + EXPECT_TRUE(ExtsRV32G.at("zmmul") == (RISCVISAUtils::ExtensionVersion{1, 0})); EXPECT_EQ(InfoRV32G.getXLen(), 32U); EXPECT_EQ(InfoRV32G.getFLen(), 64U); EXPECT_EQ(InfoRV32G.getMinVLen(), 0U); @@ -266,7 +267,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { ASSERT_THAT_EXPECTED(MaybeRV64G, Succeeded()); RISCVISAInfo &InfoRV64G = **MaybeRV64G; const auto &ExtsRV64G = InfoRV64G.getExtensions(); - EXPECT_EQ(ExtsRV64G.size(), 7UL); + EXPECT_EQ(ExtsRV64G.size(), 8UL); EXPECT_TRUE(ExtsRV64G.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1})); EXPECT_TRUE(ExtsRV64G.at("m") == (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_TRUE(ExtsRV64G.at("a") == (RISCVISAUtils::ExtensionVersion{2, 1})); @@ -275,6 +276,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { EXPECT_TRUE(ExtsRV64G.at("zicsr") == (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_TRUE(ExtsRV64G.at("zifencei") == (RISCVISAUtils::ExtensionVersion{2, 0})); + EXPECT_TRUE(ExtsRV32G.at("zmmul") == (RISCVISAUtils::ExtensionVersion{1, 0})); EXPECT_EQ(InfoRV64G.getXLen(), 64U); EXPECT_EQ(InfoRV64G.getFLen(), 64U); EXPECT_EQ(InfoRV64G.getMinVLen(), 0U); @@ -285,7 +287,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { ASSERT_THAT_EXPECTED(MaybeRV64GCV, Succeeded()); RISCVISAInfo &InfoRV64GCV = **MaybeRV64GCV; const auto &ExtsRV64GCV = InfoRV64GCV.getExtensions(); - EXPECT_EQ(ExtsRV64GCV.size(), 17UL); + EXPECT_EQ(ExtsRV64GCV.size(), 18UL); EXPECT_TRUE(ExtsRV64GCV.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1})); EXPECT_TRUE(ExtsRV64GCV.at("m") == (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_TRUE(ExtsRV64GCV.at("a") == (RISCVISAUtils::ExtensionVersion{2, 1})); @@ -295,6 +297,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { EXPECT_TRUE(ExtsRV64GCV.at("zicsr") == (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_TRUE(ExtsRV64GCV.at("zifencei") == (RISCVISAUtils::ExtensionVersion{2, 0})); + EXPECT_TRUE(ExtsRV32G.at("zmmul") == (RISCVISAUtils::ExtensionVersion{1, 0})); EXPECT_TRUE(ExtsRV64GCV.at("v") == (RISCVISAUtils::ExtensionVersion{1, 0})); EXPECT_TRUE(ExtsRV64GCV.at("zve32x") == (RISCVISAUtils::ExtensionVersion{1, 0})); EXPECT_TRUE(ExtsRV64GCV.at("zve32f") == (RISCVISAUtils::ExtensionVersion{1, 0})); @@ -424,7 +427,7 @@ TEST(ParseArchString, AcceptsUnderscoreSplittingExtensions) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); const auto &Exts = (*MaybeISAInfo)->getExtensions(); - EXPECT_EQ(Exts.size(), 8UL); + EXPECT_EQ(Exts.size(), 9UL); EXPECT_EQ(Exts.count("i"), 1U); EXPECT_EQ(Exts.count("m"), 1U); EXPECT_EQ(Exts.count("a"), 1U); @@ -433,6 +436,7 @@ TEST(ParseArchString, AcceptsUnderscoreSplittingExtensions) { EXPECT_EQ(Exts.count("c"), 1U); EXPECT_EQ(Exts.count("zicsr"), 1U); EXPECT_EQ(Exts.count("zifencei"), 1U); + EXPECT_EQ(Exts.count("zmmul"), 1U); } } @@ -442,13 +446,14 @@ TEST(ParseArchString, AcceptsRelaxSingleLetterExtensions) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); const auto &Exts = (*MaybeISAInfo)->getExtensions(); - EXPECT_EQ(Exts.size(), 6UL); + EXPECT_EQ(Exts.size(), 7UL); EXPECT_EQ(Exts.count("i"), 1U); EXPECT_EQ(Exts.count("m"), 1U); EXPECT_EQ(Exts.count("f"), 1U); EXPECT_EQ(Exts.count("a"), 1U); EXPECT_EQ(Exts.count("d"), 1U); EXPECT_EQ(Exts.count("zicsr"), 1U); + EXPECT_EQ(Exts.count("zmmul"), 1U); } } @@ -459,7 +464,7 @@ TEST(ParseArchString, AcceptsRelaxMixedLetterExtensions) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); const auto &Exts = (*MaybeISAInfo)->getExtensions(); - EXPECT_EQ(Exts.size(), 8UL); + EXPECT_EQ(Exts.size(), 9UL); EXPECT_EQ(Exts.count("i"), 1U); EXPECT_EQ(Exts.count("m"), 1U); EXPECT_EQ(Exts.count("a"), 1U); @@ -468,6 +473,7 @@ TEST(ParseArchString, AcceptsRelaxMixedLetterExtensions) { EXPECT_EQ(Exts.count("zihintntl"), 1U); EXPECT_EQ(Exts.count("svinval"), 1U); EXPECT_EQ(Exts.count("zicsr"), 1U); + EXPECT_EQ(Exts.count("zmmul"), 1U); } } @@ -476,21 +482,23 @@ TEST(ParseArchString, AcceptsAmbiguousFromRelaxExtensions) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); const auto &Exts = (*MaybeISAInfo)->getExtensions(); - EXPECT_EQ(Exts.size(), 3UL); + EXPECT_EQ(Exts.size(), 4UL); EXPECT_EQ(Exts.count("i"), 1U); EXPECT_EQ(Exts.count("zba"), 1U); EXPECT_EQ(Exts.count("m"), 1U); + EXPECT_EQ(Exts.count("zmmul"), 1U); } for (StringRef Input : {"rv32ia_zba_m", "rv32iazba_m", "rv32ia2p1zba1p0_m2p0"}) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); const auto &Exts = (*MaybeISAInfo)->getExtensions(); - EXPECT_EQ(Exts.size(), 4UL); + EXPECT_EQ(Exts.size(), 5UL); EXPECT_EQ(Exts.count("i"), 1U); EXPECT_EQ(Exts.count("zba"), 1U); EXPECT_EQ(Exts.count("m"), 1U); EXPECT_EQ(Exts.count("a"), 1U); + EXPECT_EQ(Exts.count("zmmul"), 1U); } } @@ -680,7 +688,7 @@ TEST(ParseArchString, AcceptsBareProfileNames) { auto MaybeRVA20U64 = RISCVISAInfo::parseArchString("rva20u64", true); ASSERT_THAT_EXPECTED(MaybeRVA20U64, Succeeded()); const auto &Exts = (*MaybeRVA20U64)->getExtensions(); - EXPECT_EQ(Exts.size(), 13UL); + EXPECT_EQ(Exts.size(), 14UL); EXPECT_EQ(Exts.count("i"), 1U); EXPECT_EQ(Exts.count("m"), 1U); EXPECT_EQ(Exts.count("f"), 1U); @@ -694,6 +702,7 @@ TEST(ParseArchString, AcceptsBareProfileNames) { EXPECT_EQ(Exts.count("ziccrse"), 1U); EXPECT_EQ(Exts.count("ziccamoa"), 1U); EXPECT_EQ(Exts.count("zicclsm"), 1U); + EXPECT_EQ(Exts.count("zmmul"), 1U); auto MaybeRVA23U64 = RISCVISAInfo::parseArchString("rva23u64", true); ASSERT_THAT_EXPECTED(MaybeRVA23U64, Succeeded()); @@ -704,10 +713,11 @@ TEST(ParseArchSTring, AcceptsProfileNamesWithSeparatedAdditionalExtensions) { auto MaybeRVI20U64 = RISCVISAInfo::parseArchString("rvi20u64_m_zba", true); ASSERT_THAT_EXPECTED(MaybeRVI20U64, Succeeded()); const auto &Exts = (*MaybeRVI20U64)->getExtensions(); - EXPECT_EQ(Exts.size(), 3UL); + EXPECT_EQ(Exts.size(), 4UL); EXPECT_EQ(Exts.count("i"), 1U); EXPECT_EQ(Exts.count("m"), 1U); EXPECT_EQ(Exts.count("zba"), 1U); + EXPECT_EQ(Exts.count("zmmul"), 1U); } TEST(ParseArchString, @@ -732,7 +742,7 @@ TEST(ToFeatures, IIsDroppedAndExperimentalExtensionsArePrefixed) { RISCVISAInfo::parseArchString("rv64im_ztso", true, false); ASSERT_THAT_EXPECTED(MaybeISAInfo1, Succeeded()); EXPECT_THAT((*MaybeISAInfo1)->toFeatures(), - ElementsAre("+m", "+experimental-ztso")); + ElementsAre("+m", "+zmmul", "+experimental-ztso")); auto MaybeISAInfo2 = RISCVISAInfo::parseArchString("rv32e_ztso_xventanacondops", true, false); _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
