Author: sstwcw Date: 2024-06-17T01:46:04Z New Revision: ef18986b2033a44e69b7c3553a356e9037ac1413
URL: https://github.com/llvm/llvm-project/commit/ef18986b2033a44e69b7c3553a356e9037ac1413 DIFF: https://github.com/llvm/llvm-project/commit/ef18986b2033a44e69b7c3553a356e9037ac1413.diff LOG: [clang-format] Handle Verilog delay control (#95703) I made a mistake when I tried to make the code handle the backtick character like the hash character. The code did not recognize the delay control structure. It caused net names in the declaration to be aligned to the type name instead of the first net name. new ```Verilog wire logic #0 mynet, // mynet1; ``` old ```Verilog wire logic #0 mynet, // mynet1; ``` Added: Modified: clang/lib/Format/TokenAnnotator.cpp clang/unittests/Format/FormatTestVerilog.cpp Removed: ################################################################################ diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp index 1332445070314..e5fa997387d8b 100644 --- a/clang/lib/Format/TokenAnnotator.cpp +++ b/clang/lib/Format/TokenAnnotator.cpp @@ -3414,7 +3414,8 @@ class ExpressionParser { } else { break; } - } else if (Tok->is(tok::hash)) { + } else if (Tok->is(Keywords.kw_verilogHash)) { + // Delay control. if (Next->is(tok::l_paren)) Next = Next->MatchingParen; if (Next) diff --git a/clang/unittests/Format/FormatTestVerilog.cpp b/clang/unittests/Format/FormatTestVerilog.cpp index b5241a4e0d6ae..fbaf289fbc4d6 100644 --- a/clang/unittests/Format/FormatTestVerilog.cpp +++ b/clang/unittests/Format/FormatTestVerilog.cpp @@ -391,6 +391,15 @@ TEST_F(FormatTestVerilog, Declaration) { verifyFormat("wire mynet, mynet1;"); verifyFormat("wire mynet, //\n" " mynet1;"); + verifyFormat("wire #0 mynet, mynet1;"); + verifyFormat("wire logic #0 mynet, mynet1;"); + verifyFormat("wire #(1, 2, 3) mynet, mynet1;"); + verifyFormat("wire #0 mynet, //\n" + " mynet1;"); + verifyFormat("wire logic #0 mynet, //\n" + " mynet1;"); + verifyFormat("wire #(1, 2, 3) mynet, //\n" + " mynet1;"); verifyFormat("wire mynet = enable;"); verifyFormat("wire mynet = enable, mynet1;"); verifyFormat("wire mynet = enable, //\n" _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
