[clang] [llvm] [AMDGPU] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (PR #89217)

[Matt Arsenault via cfe-commits]

================
@@ -6129,13 +6150,55 @@ static SDValue lowerLaneOp(const SITargetLowering &TLI, 
SDNode *N,
   if (ValSize % 32 != 0)
     return SDValue();
 
+  auto unrollLaneOp = [&DAG, &SL](SDNode *N) -> SDValue {
+    EVT VT = N->getValueType(0);
+    unsigned NE = VT.getVectorNumElements();
+    EVT EltVT = VT.getVectorElementType();
+    SmallVector<SDValue, 8> Scalars;
+    unsigned NumOperands = N->getNumOperands();
+    SmallVector<SDValue, 4> Operands(NumOperands);
+    SDNode *GL = N->getGluedNode();
+
+    if (GL) {
+      // only handle convegrencectrl_glue
+      assert(GL->getOpcode() == ISD::CONVERGENCECTRL_GLUE);
+    }
----------------
arsenm wrote:

Typo convegrencectrl_glue. Also assert(!GL || ...)

https://github.com/llvm/llvm-project/pull/89217
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