https://github.com/chrisnc updated
https://github.com/llvm/llvm-project/pull/88287
>From f707f292a6153f9d23734e490720db3abb5c00ac Mon Sep 17 00:00:00 2001
From: Chris Copeland <ch...@chrisnc.net>
Date: Fri, 5 Apr 2024 22:40:46 -0700
Subject: [PATCH] [ARM] Armv8-R does not require fp64 or neon.
---
clang/test/Preprocessor/arm-target-features.c | 2 +-
llvm/include/llvm/TargetParser/ARMTargetParser.def | 2 +-
llvm/lib/Target/ARM/ARM.td | 6 +++---
llvm/test/Analysis/CostModel/ARM/arith.ll | 2 +-
llvm/test/Analysis/CostModel/ARM/cast.ll | 4 ++--
llvm/test/Analysis/CostModel/ARM/cast_ldst.ll | 4 ++--
llvm/test/Analysis/CostModel/ARM/cmps.ll | 4 ++--
llvm/test/Analysis/CostModel/ARM/divrem.ll | 2 +-
llvm/test/CodeGen/ARM/build-attributes.ll | 4 ++--
llvm/test/CodeGen/ARM/cortex-a57-misched-basic.ll | 2 +-
llvm/test/CodeGen/ARM/fpconv.ll | 4 ++--
llvm/test/CodeGen/ARM/half.ll | 4 ++--
llvm/test/CodeGen/ARM/misched-fp-basic.ll | 2 +-
llvm/test/CodeGen/ARM/pr42638-VMOVRRDCombine.ll | 2 +-
llvm/test/CodeGen/ARM/useaa.ll | 4 ++--
llvm/unittests/TargetParser/TargetParserTest.cpp | 2 +-
16 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/clang/test/Preprocessor/arm-target-features.c
b/clang/test/Preprocessor/arm-target-features.c
index 236c9f2479b705..ad418bf6bcdcbf 100644
--- a/clang/test/Preprocessor/arm-target-features.c
+++ b/clang/test/Preprocessor/arm-target-features.c
@@ -96,7 +96,7 @@
// CHECK-V8R-ALLOW-FP-INSTR: #define __ARM_FEATURE_CRC32 1
// CHECK-V8R-ALLOW-FP-INSTR: #define __ARM_FEATURE_DIRECTED_ROUNDING 1
// CHECK-V8R-ALLOW-FP-INSTR: #define __ARM_FEATURE_NUMERIC_MAXMIN 1
-// CHECK-V8R-ALLOW-FP-INSTR: #define __ARM_FP 0xe
+// CHECK-V8R-ALLOW-FP-INSTR: #define __ARM_FP 0x6
// RUN: %clang -target armv7a-none-linux-gnu -x c -E -dM %s -o - | FileCheck
-match-full-lines --check-prefix=CHECK-V7 %s
// CHECK-V7: #define __ARMEL__ 1
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.def
b/llvm/include/llvm/TargetParser/ARMTargetParser.def
index b821d224d7a82c..dee0f383b4b234 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.def
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.def
@@ -329,7 +329,7 @@ ARM_CPU_NAME("cortex-r7", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
ARM_CPU_NAME("cortex-r8", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
-ARM_CPU_NAME("cortex-r52", ARMV8R, FK_NEON_FP_ARMV8, true, ARM::AEK_NONE)
+ARM_CPU_NAME("cortex-r52", ARMV8R, FK_FPV5_SP_D16, true, ARM::AEK_NONE)
ARM_CPU_NAME("sc300", ARMV7M, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-m3", ARMV7M, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-m4", ARMV7EM, FK_FPV4_SP_D16, true, ARM::AEK_NONE)
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index 66596dbda83c95..6ee8c0540e6488 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -1167,9 +1167,7 @@ def ARMv8r : Architecture<"armv8-r", "ARMv8r",
[HasV8Ops,
FeatureDSP,
FeatureCRC,
FeatureMP,
- FeatureVirtualization,
- FeatureFPARMv8,
- FeatureNEON]>;
+ FeatureVirtualization]>;
def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
[HasV8MBaselineOps,
@@ -1726,6 +1724,8 @@ def : ProcNoItin<"kryo",
[ARMv8a, ProcKryo,
FeatureCRC]>;
def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52,
+ FeatureFPARMv8_D16_SP,
+ FeatureFP16,
FeatureUseMISched,
FeatureFPAO]>;
diff --git a/llvm/test/Analysis/CostModel/ARM/arith.ll
b/llvm/test/Analysis/CostModel/ARM/arith.ll
index 3a137a5af36664..8f173596c3b9a0 100644
--- a/llvm/test/Analysis/CostModel/ARM/arith.ll
+++ b/llvm/test/Analysis/CostModel/ARM/arith.ll
@@ -4,7 +4,7 @@
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=thumbv8.1m.main-none-eabi -mattr=+mve,+mve4beat < %s | FileCheck %s
--check-prefix=CHECK --check-prefix=CHECK-MVE4
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=thumbv8m.main-none-eabi < %s | FileCheck %s
--check-prefix=CHECK-V8M-MAIN
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=thumbv8m.base-none-eabi < %s | FileCheck %s
--check-prefix=CHECK-V8M-BASE
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=armv8r-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V8R
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=armv8r-none-eabi -mattr=+neon,+fp-armv8 < %s | FileCheck %s
--check-prefix=CHECK-V8R
; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1
-disable-output -mtriple=thumbv8.1m.main -mattr=+mve < %s | FileCheck %s
--check-prefix=CHECK-MVE-SIZE
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
diff --git a/llvm/test/Analysis/CostModel/ARM/cast.ll
b/llvm/test/Analysis/CostModel/ARM/cast.ll
index 60addd3077ed14..ae0d2347ec8be0 100644
--- a/llvm/test/Analysis/CostModel/ARM/cast.ll
+++ b/llvm/test/Analysis/CostModel/ARM/cast.ll
@@ -3,11 +3,11 @@
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp < %s | FileCheck %s
--check-prefix=CHECK-MVE-RECIP
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=thumbv8m.main-none-eabi < %s | FileCheck %s
--check-prefix=CHECK-V8M-MAIN-RECIP
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=thumbv8m.base-none-eabi < %s | FileCheck %s
--check-prefix=CHECK-V8M-BASE-RECIP
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=armv8r-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V8R-RECIP
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=armv8r-none-eabi -mattr=+neon,+fp-armv8 < %s | FileCheck %s
--check-prefix=CHECK-V8R-RECIP
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-cost-kind=code-size -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp < %s |
FileCheck %s --check-prefix=CHECK-MVE-SIZE
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-cost-kind=code-size -mtriple=thumbv8m.main-none-eabi < %s | FileCheck %s
--check-prefix=CHECK-V8M-MAIN-SIZE
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-cost-kind=code-size -mtriple=thumbv8m.base-none-eabi < %s | FileCheck %s
--check-prefix=CHECK-V8M-BASE-SIZE
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-cost-kind=code-size -mtriple=armv8r-none-eabi < %s | FileCheck %s
--check-prefix=CHECK-V8R-SIZE
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-cost-kind=code-size -mtriple=armv8r-none-eabi -mattr=+neon,+fp-armv8 < %s |
FileCheck %s --check-prefix=CHECK-V8R-SIZE
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
diff --git a/llvm/test/Analysis/CostModel/ARM/cast_ldst.ll
b/llvm/test/Analysis/CostModel/ARM/cast_ldst.ll
index db700eb3baeefe..4a2f9a25dc152f 100644
--- a/llvm/test/Analysis/CostModel/ARM/cast_ldst.ll
+++ b/llvm/test/Analysis/CostModel/ARM/cast_ldst.ll
@@ -3,11 +3,11 @@
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp < %s | FileCheck %s
--check-prefix=CHECK-MVE-RECIP
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=thumbv8m.main-none-eabi < %s | FileCheck %s
--check-prefix=CHECK-V8M-MAIN-RECIP
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=thumbv8m.base-none-eabi < %s | FileCheck %s
--check-prefix=CHECK-V8M-BASE-RECIP
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=armv8r-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V8R-RECIP
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=armv8r-none-eabi -mattr=+neon,+fp-armv8 < %s | FileCheck %s
--check-prefix=CHECK-V8R-RECIP
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-cost-kind=code-size -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp < %s |
FileCheck %s --check-prefix=CHECK-MVE-SIZE
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-cost-kind=code-size -mtriple=thumbv8m.main-none-eabi < %s | FileCheck %s
--check-prefix=CHECK-V8M-MAIN-SIZE
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-cost-kind=code-size -mtriple=thumbv8m.base-none-eabi < %s | FileCheck %s
--check-prefix=CHECK-V8M-BASE-SIZE
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-cost-kind=code-size -mtriple=armv8r-none-eabi < %s | FileCheck %s
--check-prefix=CHECK-V8R-SIZE
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-cost-kind=code-size -mtriple=armv8r-none-eabi -mattr=+neon,+fp-armv8 < %s |
FileCheck %s --check-prefix=CHECK-V8R-SIZE
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
diff --git a/llvm/test/Analysis/CostModel/ARM/cmps.ll
b/llvm/test/Analysis/CostModel/ARM/cmps.ll
index 7f89f521e77cbc..184b7076d02bea 100644
--- a/llvm/test/Analysis/CostModel/ARM/cmps.ll
+++ b/llvm/test/Analysis/CostModel/ARM/cmps.ll
@@ -2,11 +2,11 @@
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp < %s | FileCheck %s
--check-prefix=CHECK-MVE-RECIP
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=thumbv8m.main-none-eabi < %s | FileCheck %s
--check-prefix=CHECK-V8M-MAIN-RECIP
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=thumbv8m.base-none-eabi < %s | FileCheck %s
--check-prefix=CHECK-V8M-BASE-RECIP
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=armv8r-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V8R-RECIP
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=armv8r-none-eabi -mattr=+neon,+fp-armv8 < %s | FileCheck %s
--check-prefix=CHECK-V8R-RECIP
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-cost-kind=code-size -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp < %s |
FileCheck %s --check-prefix=CHECK-MVE-SIZE
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-cost-kind=code-size -mtriple=thumbv8m.main-none-eabi < %s | FileCheck %s
--check-prefix=CHECK-V8M-MAIN-SIZE
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-cost-kind=code-size -mtriple=thumbv8m.base-none-eabi < %s | FileCheck %s
--check-prefix=CHECK-V8M-BASE-SIZE
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-cost-kind=code-size -mtriple=armv8r-none-eabi < %s | FileCheck %s
--check-prefix=CHECK-V8R-SIZE
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-cost-kind=code-size -mtriple=armv8r-none-eabi -mattr=+neon,+fp-armv8 < %s |
FileCheck %s --check-prefix=CHECK-V8R-SIZE
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
diff --git a/llvm/test/Analysis/CostModel/ARM/divrem.ll
b/llvm/test/Analysis/CostModel/ARM/divrem.ll
index b582a61c2a0fc8..9aba39327f6601 100644
--- a/llvm/test/Analysis/CostModel/ARM/divrem.ll
+++ b/llvm/test/Analysis/CostModel/ARM/divrem.ll
@@ -3,7 +3,7 @@
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp < %s | FileCheck %s
--check-prefix=CHECK-MVE
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=thumbv8m.main-none-eabi < %s | FileCheck %s
--check-prefix=CHECK-V8M-MAIN
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=thumbv8m.base-none-eabi < %s | FileCheck %s
--check-prefix=CHECK-V8M-BASE
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=armv8r-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V8R
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output
-mtriple=armv8r-none-eabi -mattr=+neon,+fp-armv8,+fp16 < %s | FileCheck %s
--check-prefix=CHECK-V8R
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
diff --git a/llvm/test/CodeGen/ARM/build-attributes.ll
b/llvm/test/CodeGen/ARM/build-attributes.ll
index e8c83b92f3f947..2812bf81acf98c 100644
--- a/llvm/test/CodeGen/ARM/build-attributes.ll
+++ b/llvm/test/CodeGen/ARM/build-attributes.ll
@@ -221,8 +221,8 @@
; ARMv8-R
; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52
-mattr=-vfp2sp,-fp16 | FileCheck %s --check-prefix=ARMv8R
--check-prefix=ARMv8R-NOFPU
-; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52
-mattr=-neon,-fp64,-d32 | FileCheck %s --check-prefix=ARMv8R
--check-prefix=ARMv8R-SP
-; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52 | FileCheck %s
--check-prefix=ARMv8R --check-prefix=ARMv8R-NEON
+; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52 | FileCheck %s
--check-prefix=ARMv8R --check-prefix=ARMv8R-SP
+; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52
-mattr=+neon,+fp-armv8 | FileCheck %s --check-prefix=ARMv8R
--check-prefix=ARMv8R-NEON
; ARMv8-M
; RUN: llc < %s -mtriple=thumbv8-none-none-eabi -mcpu=cortex-m23 | FileCheck
%s --check-prefix=STRICT-ALIGN
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-basic.ll
b/llvm/test/CodeGen/ARM/cortex-a57-misched-basic.ll
index 2e8a05417d4399..ec4e37f0ba804e 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-basic.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-basic.ll
@@ -1,6 +1,6 @@
; REQUIRES: asserts
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched
-verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck
%s --check-prefix=CHECK --check-prefix=A57_SCHED
-; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic -enable-misched
-verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck
%s --check-prefix=CHECK --check-prefix=GENERIC
+; RUN: llc < %s -mtriple=armv8r-eabi -mattr=+neon,+fp-armv8 -mcpu=generic
-enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 >
/dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
; Check the latency for instructions for both generic and cortex-a57.
; SDIV should be scheduled at the block's begin (20 cyc of independent M unit).
diff --git a/llvm/test/CodeGen/ARM/fpconv.ll b/llvm/test/CodeGen/ARM/fpconv.ll
index 929da5f18c813e..5dfc2a6a4629b1 100644
--- a/llvm/test/CodeGen/ARM/fpconv.ll
+++ b/llvm/test/CodeGen/ARM/fpconv.ll
@@ -1,7 +1,7 @@
; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s
--check-prefix=CHECK-VFP
; RUN: llc -mtriple=arm-apple-darwin %s -o - | FileCheck %s
-; RUN: llc -mtriple=armv8r-none-none-eabi %s -o - | FileCheck %s
--check-prefix=CHECK-VFP
-; RUN: llc -mtriple=armv8r-none-none-eabi -mattr=-fp64 %s -o - | FileCheck %s
--check-prefix=CHECK-VFP-SP
+; RUN: llc -mtriple=armv8r-none-none-eabi -mattr=+neon,+fp-armv8 %s -o - |
FileCheck %s --check-prefix=CHECK-VFP
+; RUN: llc -mtriple=armv8r-none-none-eabi -mattr=+fp-armv8,-fp64,-d32 %s -o -
| FileCheck %s --check-prefix=CHECK-VFP-SP
define float @f1(double %x) {
;CHECK-VFP-LABEL: f1:
diff --git a/llvm/test/CodeGen/ARM/half.ll b/llvm/test/CodeGen/ARM/half.ll
index 9b53dc77f22739..050b400539b4dd 100644
--- a/llvm/test/CodeGen/ARM/half.ll
+++ b/llvm/test/CodeGen/ARM/half.ll
@@ -1,8 +1,8 @@
; RUN: llc < %s -mtriple=thumbv7-apple-ios7.0 | FileCheck %s
--check-prefix=CHECK --check-prefix=CHECK-OLD
; RUN: llc < %s -mtriple=thumbv7s-apple-ios7.0 | FileCheck %s
--check-prefix=CHECK --check-prefix=CHECK-F16
; RUN: llc < %s -mtriple=thumbv8-apple-ios7.0 | FileCheck %s
--check-prefix=CHECK --check-prefix=CHECK-V8
-; RUN: llc < %s -mtriple=armv8r-none-none-eabi | FileCheck %s
--check-prefix=CHECK --check-prefix=CHECK-V8
-; RUN: llc < %s -mtriple=armv8r-none-none-eabi -mattr=-fp64 | FileCheck %s
--check-prefix=CHECK --check-prefix=CHECK-V8-SP
+; RUN: llc < %s -mtriple=armv8r-none-none-eabi -mattr=+fp-armv8,+fp16 |
FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8
+; RUN: llc < %s -mtriple=armv8r-none-none-eabi -mattr=+fp-armv8,+fp16,-fp64 |
FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8-SP
; RUN: llc < %s -mtriple=armv8.1m-none-none-eabi -mattr=+fp-armv8 | FileCheck
%s --check-prefix=CHECK --check-prefix=CHECK-V8
; RUN: llc < %s -mtriple=armv8.1m-none-none-eabi -mattr=+fp-armv8,-fp64 |
FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8-SP
; RUN: llc < %s -mtriple=armv8.1m-none-none-eabi -mattr=+mve.fp,+fp64 |
FileCheck %s --check-prefix=CHECK-V8
diff --git a/llvm/test/CodeGen/ARM/misched-fp-basic.ll
b/llvm/test/CodeGen/ARM/misched-fp-basic.ll
index 2f672b0cb540fe..203435ac642b8b 100644
--- a/llvm/test/CodeGen/ARM/misched-fp-basic.ll
+++ b/llvm/test/CodeGen/ARM/misched-fp-basic.ll
@@ -3,7 +3,7 @@
; RUN: /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_A9
; RUN: llc < %s -mtriple=arm-eabi -mcpu=swift -enable-misched -verify-misched
-debug-only=machine-scheduler -o - 2>&1 > \
; RUN: /dev/null | FileCheck %s --check-prefix=CHECK
--check-prefix=CHECK_SWIFT
-; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-r52 -enable-misched
-verify-misched -debug-only=machine-scheduler -o - 2>&1 > \
+; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-r52 -mattr=+neon,+fp-armv8
-enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > \
; RUN: /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52
;
; Check the latency of instructions for processors with sched-models
diff --git a/llvm/test/CodeGen/ARM/pr42638-VMOVRRDCombine.ll
b/llvm/test/CodeGen/ARM/pr42638-VMOVRRDCombine.ll
index 8ee88fd18f3c81..245780e6836ea2 100644
--- a/llvm/test/CodeGen/ARM/pr42638-VMOVRRDCombine.ll
+++ b/llvm/test/CodeGen/ARM/pr42638-VMOVRRDCombine.ll
@@ -16,7 +16,7 @@ entry:
declare void @llvm.va_start(ptr)
-attributes #0 = { "target-cpu"="cortex-r52" "target-features"="-fp64" }
+attributes #0 = { "target-cpu"="cortex-r52" }
; Ensures that the machine scheduler does not move accessing the upper
; 32 bits of the double to before actually storing it to memory
diff --git a/llvm/test/CodeGen/ARM/useaa.ll b/llvm/test/CodeGen/ARM/useaa.ll
index f8207a1056e3b4..bbf2bb043d3f31 100644
--- a/llvm/test/CodeGen/ARM/useaa.ll
+++ b/llvm/test/CodeGen/ARM/useaa.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 | FileCheck %s
--check-prefix=CHECK --check-prefix=USEAA
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 -mattr=+neon,+fp-armv8 |
FileCheck %s --check-prefix=CHECK --check-prefix=USEAA
; RUN: llc < %s -mtriple=armv7m-eabi -mcpu=cortex-m4 | FileCheck %s
--check-prefix=CHECK --check-prefix=USEAA
; RUN: llc < %s -mtriple=armv8m-eabi -mcpu=cortex-m33 | FileCheck %s
--check-prefix=CHECK --check-prefix=USEAA
-; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic | FileCheck %s
--check-prefix=CHECK --check-prefix=GENERIC
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic -mattr=+neon,+fp-armv8 |
FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
; Check we use AA during codegen, so can interleave these loads/stores.
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp
b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 2c72a7229b5274..82c5c0d6c12175 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -351,7 +351,7 @@ INSTANTIATE_TEST_SUITE_P(
ARM::AEK_MP | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"7-R"),
- ARMCPUTestParams<uint64_t>("cortex-r52", "armv8-r", "neon-fp-armv8",
+ ARMCPUTestParams<uint64_t>("cortex-r52", "armv8-r", "fpv5-sp-d16",
ARM::AEK_NONE | ARM::AEK_CRC | ARM::AEK_MP |
ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
