https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/84877
As discussed in https://github.com/llvm/llvm-project/pull/76357#discussion_r1518452608, we may need to add generic CPUs for profiles. I don't know if we need S-mode profile CPUs. >From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng <wangpengcheng...@bytedance.com> Date: Tue, 12 Mar 2024 14:28:09 +0800 Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?= =?UTF-8?q?l=20version?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.4 --- clang/test/Driver/riscv-cpus.c | 319 ++++++++++++++++++++++ clang/test/Misc/target-invalid-cpu-note.c | 8 +- llvm/lib/Target/RISCV/RISCVProcessors.td | 224 ++++++++++++++- 3 files changed, 539 insertions(+), 12 deletions(-) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index ff2bd6f7c8ba34..a285f0f9c41f54 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -302,3 +302,322 @@ // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64 + +// Check profile CPUs + +// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvi20u32 | FileCheck -check-prefix=MCPU-GENERIC-RVI20U32 %s +// MCPU-GENERIC-RVI20U32: "-target-cpu" "generic-rvi20u32" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-a" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-c" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-d" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-f" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-m" +// MCPU-GENERIC-RVI20U32-SAME: "-target-abi" "ilp32" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvi20u64 | FileCheck -check-prefix=MCPU-GENERIC-RVI20U64 %s +// MCPU-GENERIC-RVI20U64: "-target-cpu" "generic-rvi20u64" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-a" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-c" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-d" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-f" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-m" +// MCPU-GENERIC-RVI20U64-SAME: "-target-abi" "lp64" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20u64 | FileCheck -check-prefix=MCPU-GENERIC-RVA20U64 %s +// MCPU-GENERIC-RVA20U64: "-target-cpu" "generic-rva20u64" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+m" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+a" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+f" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+d" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+c" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccamoa" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccif" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicclsm" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccrse" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicntr" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+za128rs" +// MCPU-GENERIC-RVA20U64-SAME: "-target-abi" "lp64d" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20s64 | FileCheck -check-prefix=MCPU-GENERIC-RVA20S64 %s +// MCPU-GENERIC-RVA20S64: "-target-cpu" "generic-rva20s64" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+m" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+a" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+f" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+d" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+c" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccamoa" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccif" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicclsm" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccrse" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicntr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zifencei" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+za128rs" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ssccptr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvala" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvecd" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svade" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svbare" +// MCPU-GENERIC-RVA20S64-SAME: "-target-abi" "lp64d" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22u64 | FileCheck -check-prefix=MCPU-GENERIC-RVA22U64 %s +// MCPU-GENERIC-RVA22U64: "-target-cpu" "generic-rva22u64" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+m" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+a" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+f" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+d" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+c" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zic64b" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbom" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbop" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicboz" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+ziccamoa" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+ziccif" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicclsm" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+ziccrse" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicntr" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zihintpause" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zihpm" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+za64rs" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zfhmin" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zba" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zbb" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zbs" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zkt" +// MCPU-GENERIC-RVA22U64-SAME: "-target-abi" "lp64d" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22s64 | FileCheck -check-prefix=MCPU-GENERIC-RVA22S64 %s +// MCPU-GENERIC-RVA22S64: "-target-cpu" "generic-rva22s64" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+m" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+a" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+f" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+d" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+c" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zic64b" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicbom" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicbop" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicboz" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+ziccamoa" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+ziccif" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicclsm" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+ziccrse" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicntr" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zifencei" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zihintpause" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zihpm" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+za64rs" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zfhmin" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zba" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zbb" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zbs" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zkt" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+ssccptr" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+sscounterenw" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+sstvala" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+sstvecd" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+svade" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+svbare" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+svinval" +// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+svpbmt" +// MCPU-GENERIC-RVA22S64-SAME: "-target-abi" "lp64d" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva23u64 -menable-experimental-extensions \ +// RUN: | FileCheck -check-prefix=MCPU-GENERIC-RVA23U64 %s +// MCPU-GENERIC-RVA23U64: "-target-cpu" "generic-rva23u64" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+m" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+a" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+f" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+d" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+c" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+v" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zic64b" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicbom" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicbop" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicboz" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+ziccamoa" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+ziccif" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicclsm" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+ziccrse" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicntr" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicond" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zihintntl" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zihintpause" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zihpm" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+experimental-zimop" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+za64rs" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zawrs" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zfa" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zfhmin" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zcb" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+experimental-zcmop" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zba" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zbb" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zbs" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zkt" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zvbb" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zvfhmin" +// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zvkt" +// MCPU-GENERIC-RVA23U64-SAME: "-target-abi" "lp64d" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva23s64 -menable-experimental-extensions \ +// RUN: | FileCheck -check-prefix=MCPU-GENERIC-RVA23S64 %s +// MCPU-GENERIC-RVA23S64: "-target-cpu" "generic-rva23s64" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+m" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+a" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+f" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+d" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+c" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+v" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+h" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zic64b" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicbom" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicbop" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicboz" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ziccamoa" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ziccif" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicclsm" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ziccrse" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicntr" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicond" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zifencei" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zihintntl" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zihintpause" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zihpm" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+experimental-zimop" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+za64rs" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zawrs" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zfa" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zfhmin" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zcb" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+experimental-zcmop" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zba" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zbb" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zbs" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zkt" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zvbb" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zvfhmin" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zvkt" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shcounterenw" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shgatpa" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shtvala" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shvsatpa" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shvstvala" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shvstvecd" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ssccptr" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+sscofpmf" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+sscounterenw" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+experimental-ssnpm" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ssstateen" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+sstc" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+sstvala" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+sstvecd" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ssu64xl" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+svade" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+svbare" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+svinval" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+svnapot" +// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+svpbmt" +// MCPU-GENERIC-RVA23S64-SAME: "-target-abi" "lp64d" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvb23u64 -menable-experimental-extensions \ +// RUN: | FileCheck -check-prefix=MCPU-GENERIC-RVB23U64 %s +// MCPU-GENERIC-RVB23U64: "-target-cpu" "generic-rvb23u64" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+m" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+a" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+f" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+d" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+c" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zic64b" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicbom" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicbop" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicboz" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+ziccamoa" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+ziccif" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicclsm" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+ziccrse" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicntr" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicond" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zihintntl" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zihintpause" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zihpm" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+experimental-zimop" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+za64rs" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zawrs" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zfa" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zcb" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+experimental-zcmop" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zba" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zbb" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zbs" +// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zkt" +// MCPU-GENERIC-RVB23U64-SAME: "-target-abi" "lp64d" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvb23s64 -menable-experimental-extensions \ +// RUN: | FileCheck -check-prefix=MCPU-GENERIC-RVB23S64 %s +// MCPU-GENERIC-RVB23S64: "-target-cpu" "generic-rvb23s64" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+m" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+a" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+f" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+d" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+c" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zic64b" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicbom" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicbop" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicboz" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+ziccamoa" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+ziccif" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicclsm" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+ziccrse" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicntr" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicond" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zifencei" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zihintntl" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zihintpause" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zihpm" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+experimental-zimop" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+za64rs" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zawrs" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zfa" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zcb" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+experimental-zcmop" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zba" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zbb" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zbs" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zkt" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+ssccptr" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+sscofpmf" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+sscounterenw" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+sstc" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+sstvala" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+sstvecd" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+ssu64xl" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+svade" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+svbare" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+svinval" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+svnapot" +// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+svpbmt" +// MCPU-GENERIC-RVB23S64-SAME: "-target-abi" "lp64d" + +// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvm23u32 -menable-experimental-extensions \ +// RUN: | FileCheck -check-prefix=MCPU-GENERIC-RVM23U32 %s +// MCPU-GENERIC-RVM23U32: "-target-cpu" "generic-rvm23u32" +// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+m" +// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zicbop" +// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zicond" +// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zihintntl" +// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zihintpause" +// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+experimental-zimop" +// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zce" +// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+experimental-zcmop" +// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zba" +// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zbb" +// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zbs" +// MCPU-GENERIC-RVM23U32-SAME: "-target-abi" "ilp32" diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index b65a8fb057ee53..41347f9ed7aa14 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -81,16 +81,16 @@ // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32 // RISCV32: error: unknown target CPU 'not-a-cpu' -// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max{{$}} +// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, generic-rvi20u32, generic-rvm23u32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max{{$}} // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64 // RISCV64: error: unknown target CPU 'not-a-cpu' -// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}} +// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, generic-rva20s64, generic-rva20u64, generic-rva22s64, generic-rva22u64, generic-rva23s64, generic-rva23u64, generic-rvb23s64, generic-rvb23u64, generic-rvi20u64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}} // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, generic, rocket, sifive-7-series{{$}} +// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, generic-rvi20u32, generic-rvm23u32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, generic, rocket, sifive-7-series{{$}} // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}} +// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, generic-rva20s64, generic-rva20u64, generic-rva22s64, generic-rva22u64, generic-rva23s64, generic-rva23u64, generic-rvb23s64, generic-rvb23u64, generic-rvi20u64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}} diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 8c75df41f5e395..9c0ca06de0a5a8 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -10,6 +10,179 @@ // RISC-V processors supported. //===----------------------------------------------------------------------===// +defvar RVA20U64Features = [Feature64Bit, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZicntr, + FeatureStdExtZiccif, + FeatureStdExtZiccrse, + FeatureStdExtZiccamoa, + FeatureStdExtZa128rs, + FeatureStdExtZicclsm]; + +defvar RVA20S64Features = !listconcat(RVA20U64Features, + [FeatureStdExtZifencei, + FeatureStdExtSvbare, + FeatureStdExtSvade, + FeatureStdExtSsccptr, + FeatureStdExtSstvecd, + FeatureStdExtSstvala]); + +defvar RVA22U64Features = [Feature64Bit, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZicntr, + FeatureStdExtZiccif, + FeatureStdExtZiccrse, + FeatureStdExtZiccamoa, + FeatureStdExtZicclsm, + FeatureStdExtZa64rs, + FeatureStdExtZihpm, + FeatureStdExtZihintpause, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbs, + FeatureStdExtZic64b, + FeatureStdExtZicbom, + FeatureStdExtZicbop, + FeatureStdExtZicboz, + FeatureStdExtZfhmin, + FeatureStdExtZkt]; + +defvar RVA22S64Features = !listconcat(RVA22U64Features, + [FeatureStdExtZifencei, + FeatureStdExtSvbare, + FeatureStdExtSvade, + FeatureStdExtSsccptr, + FeatureStdExtSstvecd, + FeatureStdExtSstvala, + FeatureStdExtSscounterenw, + FeatureStdExtSvpbmt, + FeatureStdExtSvinval]); + +defvar RVA23U64Features = [Feature64Bit, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZicntr, + FeatureStdExtZihpm, + FeatureStdExtZiccif, + FeatureStdExtZiccrse, + FeatureStdExtZiccamoa, + FeatureStdExtZicclsm, + FeatureStdExtZa64rs, + FeatureStdExtZihintpause, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbs, + FeatureStdExtZic64b, + FeatureStdExtZicbom, + FeatureStdExtZicbop, + FeatureStdExtZicboz, + FeatureStdExtZfhmin, + FeatureStdExtZkt, + FeatureStdExtV, + FeatureStdExtZvfhmin, + FeatureStdExtZvbb, + FeatureStdExtZvkt, + FeatureStdExtZihintntl, + FeatureStdExtZicond, + FeatureStdExtZimop, + FeatureStdExtZcmop, + FeatureStdExtZcb, + FeatureStdExtZfa, + FeatureStdExtZawrs]; + +defvar RVA23S64Features = !listconcat(RVA23U64Features, + [FeatureStdExtZifencei, + FeatureStdExtSvbare, + FeatureStdExtSvade, + FeatureStdExtSsccptr, + FeatureStdExtSstvecd, + FeatureStdExtSstvala, + FeatureStdExtSscounterenw, + FeatureStdExtSvpbmt, + FeatureStdExtSvinval, + FeatureStdExtSvnapot, + FeatureStdExtSstc, + FeatureStdExtSscofpmf, + FeatureStdExtSsnpm, + FeatureStdExtSsu64xl, + FeatureStdExtH, + FeatureStdExtSsstateen, + FeatureStdExtShcounterenw, + FeatureStdExtShvstvala, + FeatureStdExtShtvala, + FeatureStdExtShvstvecd, + FeatureStdExtShvsatpa, + FeatureStdExtShgatpa]); + +defvar RVB23U64Features = [Feature64Bit, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZicntr, + FeatureStdExtZihpm, + FeatureStdExtZiccif, + FeatureStdExtZiccrse, + FeatureStdExtZiccamoa, + FeatureStdExtZicclsm, + FeatureStdExtZa64rs, + FeatureStdExtZihintpause, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbs, + FeatureStdExtZic64b, + FeatureStdExtZicbom, + FeatureStdExtZicbop, + FeatureStdExtZicboz, + FeatureStdExtZkt, + FeatureStdExtZihintntl, + FeatureStdExtZicond, + FeatureStdExtZimop, + FeatureStdExtZcmop, + FeatureStdExtZcb, + FeatureStdExtZfa, + FeatureStdExtZawrs]; + +defvar RVB23S64Features = !listconcat(RVB23U64Features, + [FeatureStdExtZifencei, + FeatureStdExtSvnapot, + FeatureStdExtSvbare, + FeatureStdExtSvade, + FeatureStdExtSsccptr, + FeatureStdExtSstvecd, + FeatureStdExtSstvala, + FeatureStdExtSscounterenw, + FeatureStdExtSvpbmt, + FeatureStdExtSvinval, + FeatureStdExtSstc, + FeatureStdExtSscofpmf, + FeatureStdExtSsu64xl]); + +defvar RVM23U32Features = [Feature32Bit, + FeatureStdExtM, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbs, + FeatureStdExtZicond, + FeatureStdExtZihintpause, + FeatureStdExtZihintntl, + FeatureStdExtZce, + FeatureStdExtZicbop, + FeatureStdExtZimop, + FeatureStdExtZcmop]; + class RISCVTuneInfo { bits<8> PrefFunctionAlignment = 1; bits<8> PrefLoopAlignment = 1; @@ -54,14 +227,49 @@ class RISCVTuneProcessorModel<string n, list<SubtargetFeature> f = []> : ProcessorModel<n, m, f,tunef>; -def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32", - NoSchedModel, - [Feature32Bit]>, - GenericTuneInfo; -def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64", - NoSchedModel, - [Feature64Bit]>, - GenericTuneInfo; +class RISCVGenericProcessorModel<string n, list<SubtargetFeature> f> + : RISCVProcessorModel<n, NoSchedModel, f>, + GenericTuneInfo; + +def GENERIC_RV32 : RISCVGenericProcessorModel<"generic-rv32", + [Feature32Bit]>; + +def GENERIC_RV64 : RISCVGenericProcessorModel<"generic-rv64", + [Feature64Bit]>; + +def GENERIC_RVI20U32 : RISCVGenericProcessorModel<"generic-rvi20u32", + [Feature32Bit]>; + +def GENERIC_RVI20U64 : RISCVGenericProcessorModel<"generic-rvi20u64", + [Feature64Bit]>; + +def GENERIC_RVA20U64 : RISCVGenericProcessorModel<"generic-rva20u64", + RVA20U64Features>; + +def GENERIC_RVA20S64 : RISCVGenericProcessorModel<"generic-rva20s64", + RVA20S64Features>; + +def GENERIC_RVA22U64 : RISCVGenericProcessorModel<"generic-rva22u64", + RVA22U64Features>; + +def GENERIC_RVA22S64 : RISCVGenericProcessorModel<"generic-rva22s64", + RVA22S64Features>; + +def GENERIC_RVA23U64 : RISCVGenericProcessorModel<"generic-rva23u64", + RVA23U64Features>; + +def GENERIC_RVA23S64 : RISCVGenericProcessorModel<"generic-rva23s64", + RVA23S64Features>; + +def GENERIC_RVB23U64 : RISCVGenericProcessorModel<"generic-rvb23u64", + RVB23U64Features>; + +def GENERIC_RVB23S64 : RISCVGenericProcessorModel<"generic-rvb23s64", + RVB23S64Features>; + +def GENERIC_RVM23U32 : RISCVGenericProcessorModel<"generic-rvm23u32", + RVM23U32Features>; + // Support generic for compatibility with other targets. The triple will be used // to change to the appropriate rv32/rv64 version. def : ProcessorModel<"generic", NoSchedModel, []>, GenericTuneInfo; _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
