iid_iunknown created this revision.
iid_iunknown added a reviewer: LukeCheeseman.
iid_iunknown added a subscriber: cfe-commits.
iid_iunknown set the repository for this revision to rL LLVM.
Herald added subscribers: rengolin, aemerson.
This is a simple sema check patch for arguments of `__builtin_arm_rsr` and the
related builtins, which currently do not allow special registers with indexes
>7.
Some of the possible register name formats these builtins accept are:
{c}p<coprocessor>:<op1>:c<CRn>:c<CRm>:<op2>
o0:op1:CRn:CRm:op2
where `op1` / `op2` are integers in the range [0, 7] and `CRn` / `CRm` are
integers in the range [0, 15].
The current sema check does not allow `CRn` > 7 and accepts `op2` up to 15.
Repository:
rL LLVM
https://reviews.llvm.org/D26464
Files:
lib/Sema/SemaChecking.cpp
Index: lib/Sema/SemaChecking.cpp
===================================================================
--- lib/Sema/SemaChecking.cpp
+++ lib/Sema/SemaChecking.cpp
@@ -4191,7 +4191,7 @@
SmallVector<int, 5> Ranges;
if (FiveFields)
- Ranges.append({IsAArch64Builtin ? 1 : 15, 7, 7, 15, 15});
+ Ranges.append({IsAArch64Builtin ? 1 : 15, 7, 15, 15, 7});
else
Ranges.append({15, 7, 15});
Index: lib/Sema/SemaChecking.cpp
===================================================================
--- lib/Sema/SemaChecking.cpp
+++ lib/Sema/SemaChecking.cpp
@@ -4191,7 +4191,7 @@
SmallVector<int, 5> Ranges;
if (FiveFields)
- Ranges.append({IsAArch64Builtin ? 1 : 15, 7, 7, 15, 15});
+ Ranges.append({IsAArch64Builtin ? 1 : 15, 7, 15, 15, 7});
else
Ranges.append({15, 7, 15});
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