================
@@ -355,6 +356,18 @@ class SICacheControl {
MachineBasicBlock::iterator &MI) const {
return false;
}
+
+public:
+ // The following is for supporting precise memory mode. When the option
+ // amdgpu-precise-memory is enabled, an s_waitcnt instruction is inserted
+ // after each memory instruction.
+
+ virtual bool
+ handleNonAtomicForPreciseMemory(MachineBasicBlock::iterator &MI) = 0;
+ /// Handles atomic instruction \p MI with \p IsAtomicWithRet indicating
+ /// whether \p MI returns a result.
----------------
jwanggit86 wrote:
Adding the comments is mainly to be consistent with the existing code. Here the
comment points out that the 2nd parameter is a property of the first parameter
(MI), which is not absolutely clear by just looking at the code.
https://github.com/llvm/llvm-project/pull/79236
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