================
@@ -82,6 +88,13 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
return is64Bit() ? 2047 : 0;
}
+ bool isRegisterReserved(MCPhysReg PhysReg) const {
+ if (PhysReg >= SP::G0 && PhysReg <= SP::O7)
+ return ReserveRegister[PhysReg - SP::G0];
----------------
koachan wrote:
The main issue here I think is that during
[initalizaion](https://github.com/llvm/llvm-project/pull/74927/files#diff-f3eeee787e92610d3bbd061545a650aca73d629b23a6e6b98c72e499fbd66787R53)
I'm not sure which value do I need to pull to get all the registers defined in
the td files.
Would `SP::NUM_TARGET_REGS` be enough?
https://github.com/llvm/llvm-project/pull/74927
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