llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: Brandon Wu (4vtomat) <details> <summary>Changes</summary> This patch models LMUL and SEW as inputs in sf_vc_x_se and sf_vc_i_se, it reduces 42 intrinsics in the lookup table. --- Patch is 125.78 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/79407.diff 13 Files Affected: - (modified) clang/include/clang/Basic/riscv_sifive_vector.td (+9-20) - (modified) clang/lib/Headers/sifive_vector.h (+102) - (modified) clang/lib/Sema/SemaChecking.cpp (+8-48) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x-rv64.c (+8-4) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x.c (+106-80) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/xsfvcp-index-out-of-range.c (+7-7) - (modified) llvm/include/llvm/IR/IntrinsicsRISCVXsf.td (+24-20) - (modified) llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (+64) - (modified) llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h (+2) - (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (-88) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td (-14) - (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-x.ll (+80-80) - (modified) llvm/test/CodeGen/RISCV/rvv/xsfvcp-x.ll (+80-80) ``````````diff diff --git a/clang/include/clang/Basic/riscv_sifive_vector.td b/clang/include/clang/Basic/riscv_sifive_vector.td index ef5114d6105e48a..0761712a40fbafb 100644 --- a/clang/include/clang/Basic/riscv_sifive_vector.td +++ b/clang/include/clang/Basic/riscv_sifive_vector.td @@ -46,34 +46,23 @@ multiclass VCIXBuiltinSet<string name, string IR_name, string suffix, } multiclass RVVVCIXBuiltinSet<list<string> range, string prototype, - list<int> intrinsic_types, bit UseGPR> { + list<int> intrinsic_types, bit UseGPR, + string suffix = "Uv"> { foreach r = range in let RequiredFeatures = !if(!and(UseGPR, !eq(r, "l")), ["Xsfvcp", "RV64"], ["Xsfvcp"]) in - defm : VCIXBuiltinSet<NAME, NAME, "Uv", prototype, r, intrinsic_types>; + defm : VCIXBuiltinSet<NAME, NAME, suffix, prototype, r, intrinsic_types>; } -multiclass RVVVCIXBuiltinSetWVType<list<string> range, string prototype, - list<int> intrinsic_types, bit UseGPR> { - foreach r = range in - let RequiredFeatures = !if(!and(UseGPR, !eq(r, "l")), - ["Xsfvcp", "RV64"], ["Xsfvcp"]) in - // These intrinsics don't have any vector types in the output and inputs, - // but we still need to add vetvli for them. So we encode different - // VTYPE into the intrinsic names, and then will know which vsetvli is - // correct. - foreach s = VCIXSuffix<r>.suffix in - // Since we already encode the Vtype into the name, so just set - // Log2LMUL to zero. Otherwise the RISCVVEmitter will expand - // lots of redundant intrinsic but have same names. - let Log2LMUL = [0] in - def : VCIXBuiltinSet<NAME # "_u" # s, NAME # "_e" # s, - "", prototype, r, intrinsic_types>; +multiclass RVVVCIXBuiltinSetWOSuffix<list<string> range, string prototype, + list<int> intrinsic_types, bit UseGPR> { + let Log2LMUL = [0] in + defm NAME : RVVVCIXBuiltinSet<range, prototype, intrinsic_types, UseGPR, "">; } let SupportOverloading = false in { - defm sf_vc_x_se : RVVVCIXBuiltinSetWVType<["c", "s", "i", "l"], "0KzKzKzUe", [0, 3], UseGPR=1>; - defm sf_vc_i_se : RVVVCIXBuiltinSetWVType<["c", "s", "i", "l"], "0KzKzKzKz", [2, 3], UseGPR=0>; + defm sf_vc_x : RVVVCIXBuiltinSetWOSuffix<["i"], "0KzKzKzUeKzKz", [0, 3], UseGPR=1>; + defm sf_vc_i : RVVVCIXBuiltinSetWOSuffix<["i"], "0KzKzKzKzKzKz", [2, 3], UseGPR=0>; defm sf_vc_xv : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvUe", [0, 2, 3], UseGPR=1>; defm sf_vc_iv : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvKz", [0, 2, 3], UseGPR=0>; defm sf_vc_vv : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvUv", [0, 2, 3], UseGPR=0>; diff --git a/clang/lib/Headers/sifive_vector.h b/clang/lib/Headers/sifive_vector.h index 42d7224db614541..2dea69947754acc 100644 --- a/clang/lib/Headers/sifive_vector.h +++ b/clang/lib/Headers/sifive_vector.h @@ -13,4 +13,106 @@ #pragma clang riscv intrinsic sifive_vector +#define __riscv_sf_vc_x_se_u8mf4(p27_26, p24_20, p11_7, rs1, vl) \ + __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 8, 6, vl) +#define __riscv_sf_vc_x_se_u8mf2(p27_26, p24_20, p11_7, rs1, vl) \ + __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 8, 7, vl) +#define __riscv_sf_vc_x_se_u8m1(p27_26, p24_20, p11_7, rs1, vl) \ + __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 8, 0, vl) +#define __riscv_sf_vc_x_se_u8m2(p27_26, p24_20, p11_7, rs1, vl) \ + __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 8, 1, vl) +#define __riscv_sf_vc_x_se_u8m4(p27_26, p24_20, p11_7, rs1, vl) \ + __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 8, 2, vl) +#define __riscv_sf_vc_x_se_u8m8(p27_26, p24_20, p11_7, rs1, vl) \ + __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 8, 3, vl) + +#define __riscv_sf_vc_x_se_u16mf2(p27_26, p24_20, p11_7, rs1, vl) \ + __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 16, 7, vl) +#define __riscv_sf_vc_x_se_u16m1(p27_26, p24_20, p11_7, rs1, vl) \ + __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 16, 0, vl) +#define __riscv_sf_vc_x_se_u16m2(p27_26, p24_20, p11_7, rs1, vl) \ + __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 16, 1, vl) +#define __riscv_sf_vc_x_se_u16m4(p27_26, p24_20, p11_7, rs1, vl) \ + __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 16, 2, vl) +#define __riscv_sf_vc_x_se_u16m8(p27_26, p24_20, p11_7, rs1, vl) \ + __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 16, 3, vl) + +#define __riscv_sf_vc_x_se_u32m1(p27_26, p24_20, p11_7, rs1, vl) \ + __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 32, 0, vl) +#define __riscv_sf_vc_x_se_u32m2(p27_26, p24_20, p11_7, rs1, vl) \ + __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 32, 1, vl) +#define __riscv_sf_vc_x_se_u32m4(p27_26, p24_20, p11_7, rs1, vl) \ + __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 32, 2, vl) +#define __riscv_sf_vc_x_se_u32m8(p27_26, p24_20, p11_7, rs1, vl) \ + __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 32, 3, vl) + +#define __riscv_sf_vc_i_se_u8mf4(p27_26, p24_20, p11_7, simm5, vl) \ + __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 7, vl) +#define __riscv_sf_vc_i_se_u8mf2(p27_26, p24_20, p11_7, simm5, vl) \ + __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 6, vl) +#define __riscv_sf_vc_i_se_u8m1(p27_26, p24_20, p11_7, simm5, vl) \ + __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 0, vl) +#define __riscv_sf_vc_i_se_u8m2(p27_26, p24_20, p11_7, simm5, vl) \ + __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 1, vl) +#define __riscv_sf_vc_i_se_u8m4(p27_26, p24_20, p11_7, simm5, vl) \ + __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 2, vl) +#define __riscv_sf_vc_i_se_u8m8(p27_26, p24_20, p11_7, simm5, vl) \ + __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 3, vl) + +#define __riscv_sf_vc_i_se_u16mf2(p27_26, p24_20, p11_7, simm5, vl) \ + __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 16, 7, vl) +#define __riscv_sf_vc_i_se_u16m1(p27_26, p24_20, p11_7, simm5, vl) \ + __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 16, 0, vl) +#define __riscv_sf_vc_i_se_u16m2(p27_26, p24_20, p11_7, simm5, vl) \ + __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 16, 1, vl) +#define __riscv_sf_vc_i_se_u16m4(p27_26, p24_20, p11_7, simm5, vl) \ + __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 16, 2, vl) +#define __riscv_sf_vc_i_se_u16m8(p27_26, p24_20, p11_7, simm5, vl) \ + __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 16, 3, vl) + +#define __riscv_sf_vc_i_se_u32m1(p27_26, p24_20, p11_7, simm5, vl) \ + __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 32, 0, vl) +#define __riscv_sf_vc_i_se_u32m2(p27_26, p24_20, p11_7, simm5, vl) \ + __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 32, 1, vl) +#define __riscv_sf_vc_i_se_u32m4(p27_26, p24_20, p11_7, simm5, vl) \ + __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 32, 2, vl) +#define __riscv_sf_vc_i_se_u32m8(p27_26, p24_20, p11_7, simm5, vl) \ + __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 32, 3, vl) + +#if __riscv_v_elen >= 64 +#define __riscv_sf_vc_x_se_u8mf8(p27_26, p24_20, p11_7, rs1, vl) \ + __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 8, 5, vl) +#define __riscv_sf_vc_x_se_u16mf4(p27_26, p24_20, p11_7, rs1, vl) \ + __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 16, 6, vl) +#define __riscv_sf_vc_x_se_u32mf2(p27_26, p24_20, p11_7, rs1, vl) \ + __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 32, 7, vl) + +#define __riscv_sf_vc_i_se_u8mf8(p27_26, p24_20, p11_7, simm5, vl) \ + __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 5, vl) +#define __riscv_sf_vc_i_se_u16mf4(p27_26, p24_20, p11_7, simm5, vl) \ + __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 16, 6, vl) +#define __riscv_sf_vc_i_se_u32mf2(p27_26, p24_20, p11_7, simm5, vl) \ + __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 32, 7, vl) + +#define __riscv_sf_vc_i_se_u64m1(p27_26, p24_20, p11_7, simm5, vl) \ + __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 64, 0, vl) +#define __riscv_sf_vc_i_se_u64m2(p27_26, p24_20, p11_7, simm5, vl) \ + __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 64, 1, vl) +#define __riscv_sf_vc_i_se_u64m4(p27_26, p24_20, p11_7, simm5, vl) \ + __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 64, 2, vl) +#define __riscv_sf_vc_i_se_u64m8(p27_26, p24_20, p11_7, simm5, vl) \ + __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 64, 3, vl) + +#if __riscv_xlen >= 64 +#define __riscv_sf_vc_x_se_u64m1(p27_26, p24_20, p11_7, rs1, vl) \ + __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 64, 0, vl) +#define __riscv_sf_vc_x_se_u64m2(p27_26, p24_20, p11_7, rs1, vl) \ + __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 64, 1, vl) +#define __riscv_sf_vc_x_se_u64m4(p27_26, p24_20, p11_7, rs1, vl) \ + __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 64, 2, vl) +#define __riscv_sf_vc_x_se_u64m8(p27_26, p24_20, p11_7, rs1, vl) \ + __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 64, 3, vl) +#endif +#endif + #endif //_SIFIVE_VECTOR_H_ diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 4d280f25cc04c25..ad8a1235f9d22b1 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -5441,33 +5441,13 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, CheckInvalidVLENandLMUL(TI, TheCall, *this, Op3Type, ElemSize * 4); } - case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8mf8: - case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8mf4: - case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8mf2: - case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8m1: - case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8m2: - case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8m4: - case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8m8: - case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16mf4: - case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16mf2: - case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16m1: - case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16m2: - case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16m4: - case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16m8: - case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u32mf2: - case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u32m1: - case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u32m2: - case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u32m4: - case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u32m8: - case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u64m1: - case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u64m2: - case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u64m4: - case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u64m8: - // bit_27_26, bit_24_20, bit_11_7, simm5 + case RISCVVector::BI__builtin_rvv_sf_vc_i_se: + // bit_27_26, bit_24_20, bit_11_7, simm5, sew, log2lmul return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) || SemaBuiltinConstantArgRange(TheCall, 1, 0, 31) || SemaBuiltinConstantArgRange(TheCall, 2, 0, 31) || - SemaBuiltinConstantArgRange(TheCall, 3, -16, 15); + SemaBuiltinConstantArgRange(TheCall, 3, -16, 15) || + CheckRISCVLMUL(TheCall, 5); case RISCVVector::BI__builtin_rvv_sf_vc_iv_se: // bit_27_26, bit_11_7, vs2, simm5 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) || @@ -5493,32 +5473,12 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, // bit_27_26, vd, vs2, simm5 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) || SemaBuiltinConstantArgRange(TheCall, 3, -16, 15); - case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8mf8: - case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8mf4: - case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8mf2: - case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8m1: - case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8m2: - case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8m4: - case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8m8: - case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16mf4: - case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16mf2: - case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16m1: - case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16m2: - case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16m4: - case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16m8: - case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u32mf2: - case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u32m1: - case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u32m2: - case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u32m4: - case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u32m8: - case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u64m1: - case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u64m2: - case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u64m4: - case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u64m8: - // bit_27_26, bit_24_20, bit_11_7, xs1 + case RISCVVector::BI__builtin_rvv_sf_vc_x_se: + // bit_27_26, bit_24_20, bit_11_7, xs1, sew, log2lmul return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) || SemaBuiltinConstantArgRange(TheCall, 1, 0, 31) || - SemaBuiltinConstantArgRange(TheCall, 2, 0, 31); + SemaBuiltinConstantArgRange(TheCall, 2, 0, 31) || + CheckRISCVLMUL(TheCall, 5); case RISCVVector::BI__builtin_rvv_sf_vc_xv_se: case RISCVVector::BI__builtin_rvv_sf_vc_vv_se: // bit_27_26, bit_11_7, vs2, xs1/vs1 diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x-rv64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x-rv64.c index fe6972dc7942f16..742b87f7b0d3a04 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x-rv64.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x-rv64.c @@ -10,7 +10,8 @@ // CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e64m1.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[CONV:%.*]] = trunc i64 [[RS1:%.*]] to i32 +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i32.i64(i64 3, i64 31, i64 31, i32 [[CONV]], i64 64, i64 0, i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret void // void test_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) { @@ -19,7 +20,8 @@ void test_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) { // CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e64m2.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[CONV:%.*]] = trunc i64 [[RS1:%.*]] to i32 +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i32.i64(i64 3, i64 31, i64 31, i32 [[CONV]], i64 64, i64 1, i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret void // void test_sf_vc_x_se_u64m2(uint64_t rs1, size_t vl) { @@ -28,7 +30,8 @@ void test_sf_vc_x_se_u64m2(uint64_t rs1, size_t vl) { // CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e64m4.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[CONV:%.*]] = trunc i64 [[RS1:%.*]] to i32 +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i32.i64(i64 3, i64 31, i64 31, i32 [[CONV]], i64 64, i64 2, i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret void // void test_sf_vc_x_se_u64m4(uint64_t rs1, size_t vl) { @@ -37,7 +40,8 @@ void test_sf_vc_x_se_u64m4(uint64_t rs1, size_t vl) { // CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e64m8.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[CONV:%.*]] = trunc i64 [[RS1:%.*]] to i32 +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i32.i64(i64 3, i64 31, i64 31, i32 [[CONV]], i64 64, i64 3, i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret void // void test_sf_vc_x_se_u64m8(uint64_t rs1, size_t vl) { diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x.c index bac7e019c35b199..25703154b5ec2c8 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x.c @@ -12,12 +12,14 @@ // CHECK-RV32-LABEL: @test_sf_vc_x_se_u8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.e8mf8.i32.i8.i32(i32 3, i32 31, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[CONV:%.*]] = zext i8 [[RS1:%.*]] to i32 +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 [[CONV]], i32 8, i32 5, i32 [[VL:%.*]]) // CHECK-RV32-NEXT: ret void // // CHECK-RV64-LABEL: @test_sf_vc_x_se_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e8mf8.i64.i8.i64(i64 3, i64 31, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[CONV:%.*]] = zext i8 [[RS1:%.*]] to i32 +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i32.i64(i64 3, i64 31, i64 31, i32 [[CONV]], i64 8, i64 5, i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret void // void test_sf_vc_x_se_u8mf8(uint8_t rs1, size_t vl) { @@ -26,12 +28,14 @@ void test_sf_vc_x_se_u8mf8(uint8_t rs1, size_t vl) { // CHECK-RV32-LABEL: @test_sf_vc_x_se_u8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.e8mf4.i32.i8.i32(i32 3, i32 31, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[CONV:%.*]] = zext i8 [[RS1:%.*]] to i32 +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 [[CONV]], i32 8, i32 6, i32 [[VL:%.*]]) // CHECK-RV32-NEXT: ret void // // CHECK-RV64-LABEL: @test_sf_vc_x_se_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e8mf4.i64.i8.i64(i64 3, i64 31, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[CONV:%.*]] = zext i8 [[RS1:%.*]] to i32 +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i32.i64(i64 3, i64 31, i64 31, i32 [[CONV]], i64 8, i64 6, i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret void // void test_sf_vc_x_se_u8mf4(uint8_t rs1, size_t vl) { @@ -40,12 +44,14 @@ void test_sf_vc_x_se_u8mf4(uint8_t rs1, size_t vl) { // CHECK-RV32-LABEL: @test_sf_vc_x_se_u8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.e8mf2.i32.i8.i32(i32 3, i32 31, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[CONV:%.*]] = zext i8 [[RS1:%.*]] to i32 +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 [[CONV]], i32 8, i32 7, i32 [[VL:%.*]]) // CHECK-RV32-NEXT: ret void // // CHECK-RV64-LABEL: @test_sf_vc_x_se_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e8mf2.i64.i8.i64(i64 3, i64 31, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[CONV:%.*]] = zext i8 [[RS1:%.*]] to i32 +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i32.i64(i64 3, i64 31, i64 31, i32 [[CONV]], i64 8, i64 7, i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret void // void test_sf_vc_x_se_u8mf2(uint8_t rs1, size_t vl) { @@ -54,12 +60,14 @@ void test_sf_vc_x_se_u8mf2(uint8_t rs1, size_t vl) { // CHECK-RV32-LABEL: @test_sf_vc_x_se_u8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.e8m1.i32.i8.i32(i32 3, i32 31, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[CONV:%.*]] = zext i8 [[RS1:%.*]] to i32 +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 [[CONV]], i32 8, i32 0, i32 [[VL:%.*]]) // CHECK-RV32-NEXT... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/79407 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
