llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: Michael Maitland (michaelmaitland) <details> <summary>Changes</summary> This is an OOO core that has a vector unit. For more information see https://www.sifive.com/cores/performance-p650-670. Scheduler model and other tuning will come in separate patches. --- Patch is 23.27 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/79015.diff 6 Files Affected: - (modified) clang/test/Driver/riscv-cpus.c (+11-1) - (modified) clang/test/Misc/target-invalid-cpu-note.c (+2-2) - (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+7) - (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+8) - (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+37) - (added) llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll (+353) ``````````diff diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index d181755bb585070..666a3e2beabeb1e 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -241,7 +241,17 @@ // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbb" // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs" // MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d" -// + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck -check-prefix=MCPU-SIFIVE-P670 %s +// MCPU-SIFIVE-P670: "-target-cpu" "sifive-p670" +// MCPU-SIFIVE-P670-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" +// MCPU-SIFIVE-P670-SAME: "-target-feature" "+c" "-target-feature" "+v" "-target-feature" "+zic64b" "-target-feature" "+zicbom" "-target-feature" "+zicbop" "-target-feature" "+zicboz" "-target-feature" "+ziccamoa" "-target-feature" "+ziccif" "-target-feature" "+zicclsm" "-target-feature" "+ziccrse" "-target-feature" "+zicsr" "-target-feature" "+zifencei" "-target-feature" "+zihintntl" "-target-feature" "+zihintpause" "-target-feature" "+zihpm" "-target-feature" "+za64rs" "-target-feature" "+zfhmin" +// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zba" "-target-feature" "+zbb" "-target-feature" "+zbs" +// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvbb" "-target-feature" "+zvbc" +// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve32f" "-target-feature" "+zve32x" "-target-feature" "+zve64d" "-target-feature" "+zve64f" "-target-feature" "+zve64x" +// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkg" "-target-feature" "+zvkn" "-target-feature" "+zvknc" "-target-feature" "+zvkned" "-target-feature" "+zvkng" "-target-feature" "+zvknhb" "-target-feature" "+zvks" "-target-feature" "+zvksc" "-target-feature" "+zvksed" "-target-feature" "+zvksg" "-target-feature" "+zvksh" "-target-feature" "+zvkt" +// MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d" + // Check failed cases // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | FileCheck -check-prefix=FAIL-MCPU-NAME %s diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index 48e9f05d9b03de2..84aed5c9c36fe47 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -85,7 +85,7 @@ // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64 // RISCV64: error: unknown target CPU 'not-a-cpu' -// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}} +// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}} // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu' @@ -93,4 +93,4 @@ // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}} +// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}} diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index cbb096ba20ae67b..04ee6d6d0547378 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1082,6 +1082,13 @@ def TuneShortForwardBranchOpt def HasShortForwardBranchOpt : Predicate<"Subtarget->hasShortForwardBranchOpt()">; def NoShortForwardBranchOpt : Predicate<"!Subtarget->hasShortForwardBranchOpt()">; +// P670 requires a S2V transfer buffer to move scalars into vectors. +// FIXME: Forming .vx/.vf can reduce register pressure. +def TuneDontSinkSplatOperands + : SubtargetFeature<"dont-sink-splat-operands", "DontSinkSplatOperands", + "true", "Don't sink splat operands to enable .vx or .vf " + "instructions">; + def TuneConditionalCompressedMoveFusion : SubtargetFeature<"conditional-cmv-fusion", "HasConditionalCompressedMoveFusion", "true", "Enable branch+c.mv fusion">; diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index b41e2f40dc72f01..6737f1c16238909 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -2000,6 +2000,14 @@ bool RISCVTargetLowering::shouldSinkOperands( if (!I->getType()->isVectorTy() || !Subtarget.hasVInstructions()) return false; + // Don't sink splat operands if the target prefers it. Some targets requires + // S2V transfer buffers and we can run out of them copying the same value + // repeatedly. + // FIXME: It could still be worth doing if it would improve vector register + // pressure and prevent a vector spill. + if (Subtarget.dontSinkSplatOperands()) + return false; + for (auto OpIdx : enumerate(I->operands())) { if (!canSplatOperand(I, OpIdx.index())) continue; diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index d1cd9ba1dd84d1b..c7425de99dc132c 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -237,6 +237,43 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model, TuneLUIADDIFusion, TuneAUIPCADDIFusion]>; +def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", NoSchedModel, + [Feature64Bit, + FeatureStdExtZifencei, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZa64rs, + FeatureStdExtZic64b, + FeatureStdExtZicbop, + FeatureStdExtZicbom, + FeatureStdExtZicboz, + FeatureStdExtZiccamoa, + FeatureStdExtZiccif, + FeatureStdExtZicclsm, + FeatureStdExtZiccrse, + FeatureStdExtZihintntl, + FeatureStdExtZihintpause, + FeatureStdExtZihpm, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbs, + FeatureStdExtZfhmin, + FeatureStdExtV, + FeatureStdExtZvl128b, + FeatureStdExtZvbb, + FeatureStdExtZvknc, + FeatureStdExtZvkng, + FeatureStdExtZvksc, + FeatureStdExtZvksg, + FeatureFastUnalignedAccess], + [TuneNoDefaultUnroll, + TuneConditionalCompressedMoveFusion, + TuneLUIADDIFusion, + TuneDontSinkSplatOperands]>; + def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base", SyntacoreSCR1Model, [Feature32Bit, diff --git a/llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll b/llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll new file mode 100644 index 000000000000000..88eac06294240c4 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll @@ -0,0 +1,353 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+f -target-abi=lp64f \ +; RUN: -mattr=+dont-sink-splat-operands -riscv-v-vector-bits-min=128 | FileCheck %s + +; Test that we don't sink splat operands when compiling with dont-sink-splat-operands. +; Each scalar register access requires a S2V transfer buffer entry. Using too many +; limits performance. +; FIXME: This is potentially bad for register pressure. Need a better heuristic. + +define void @sink_splat_add(i32* nocapture %a, i32 signext %x) { +; CHECK-LABEL: sink_splat_add: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: li a1, 1024 +; CHECK-NEXT: .LBB0_1: # %vector.body +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vle32.v v9, (a0) +; CHECK-NEXT: vadd.vv v9, v9, v8 +; CHECK-NEXT: vse32.v v9, (a0) +; CHECK-NEXT: addi a1, a1, -4 +; CHECK-NEXT: addi a0, a0, 16 +; CHECK-NEXT: bnez a1, .LBB0_1 +; CHECK-NEXT: # %bb.2: # %for.cond.cleanup +; CHECK-NEXT: ret +entry: + %broadcast.splatinsert = insertelement <4 x i32> poison, i32 %x, i32 0 + %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds i32, i32* %a, i64 %index + %1 = bitcast i32* %0 to <4 x i32>* + %wide.load = load <4 x i32>, <4 x i32>* %1, align 4 + %2 = add <4 x i32> %wide.load, %broadcast.splat + %3 = bitcast i32* %0 to <4 x i32>* + store <4 x i32> %2, <4 x i32>* %3, align 4 + %index.next = add nuw i64 %index, 4 + %4 = icmp eq i64 %index.next, 1024 + br i1 %4, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body + ret void +} + +declare i64 @llvm.vscale.i64() + +define void @sink_splat_add_scalable(i32* nocapture %a, i32 signext %x) { +; CHECK-LABEL: sink_splat_add_scalable: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a5, vlenb +; CHECK-NEXT: srli a3, a5, 1 +; CHECK-NEXT: li a2, 1024 +; CHECK-NEXT: bgeu a2, a3, .LBB1_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: li a2, 0 +; CHECK-NEXT: j .LBB1_5 +; CHECK-NEXT: .LBB1_2: # %vector.ph +; CHECK-NEXT: addi a2, a3, -1 +; CHECK-NEXT: andi a4, a2, 1024 +; CHECK-NEXT: xori a2, a4, 1024 +; CHECK-NEXT: vsetvli a6, zero, e32, m2, ta, ma +; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: slli a5, a5, 1 +; CHECK-NEXT: mv a6, a0 +; CHECK-NEXT: mv a7, a2 +; CHECK-NEXT: .LBB1_3: # %vector.body +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vl2re32.v v10, (a6) +; CHECK-NEXT: vadd.vv v10, v10, v8 +; CHECK-NEXT: vs2r.v v10, (a6) +; CHECK-NEXT: sub a7, a7, a3 +; CHECK-NEXT: add a6, a6, a5 +; CHECK-NEXT: bnez a7, .LBB1_3 +; CHECK-NEXT: # %bb.4: # %middle.block +; CHECK-NEXT: beqz a4, .LBB1_7 +; CHECK-NEXT: .LBB1_5: # %for.body.preheader +; CHECK-NEXT: addi a3, a2, -1024 +; CHECK-NEXT: slli a2, a2, 2 +; CHECK-NEXT: add a0, a0, a2 +; CHECK-NEXT: .LBB1_6: # %for.body +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: lw a2, 0(a0) +; CHECK-NEXT: add a2, a2, a1 +; CHECK-NEXT: sw a2, 0(a0) +; CHECK-NEXT: addi a3, a3, 1 +; CHECK-NEXT: addi a0, a0, 4 +; CHECK-NEXT: bnez a3, .LBB1_6 +; CHECK-NEXT: .LBB1_7: # %for.cond.cleanup +; CHECK-NEXT: ret +entry: + %0 = call i64 @llvm.vscale.i64() + %1 = shl i64 %0, 2 + %min.iters.check = icmp ugt i64 %1, 1024 + br i1 %min.iters.check, label %for.body.preheader, label %vector.ph + +vector.ph: ; preds = %entry + %2 = call i64 @llvm.vscale.i64() + %3 = shl i64 %2, 2 + %n.mod.vf = urem i64 1024, %3 + %n.vec = sub nsw i64 1024, %n.mod.vf + %broadcast.splatinsert = insertelement <vscale x 4 x i32> poison, i32 %x, i32 0 + %broadcast.splat = shufflevector <vscale x 4 x i32> %broadcast.splatinsert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer + %4 = call i64 @llvm.vscale.i64() + %5 = shl i64 %4, 2 + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %6 = getelementptr inbounds i32, i32* %a, i64 %index + %7 = bitcast i32* %6 to <vscale x 4 x i32>* + %wide.load = load <vscale x 4 x i32>, <vscale x 4 x i32>* %7, align 4 + %8 = add <vscale x 4 x i32> %wide.load, %broadcast.splat + %9 = bitcast i32* %6 to <vscale x 4 x i32>* + store <vscale x 4 x i32> %8, <vscale x 4 x i32>* %9, align 4 + %index.next = add nuw i64 %index, %5 + %10 = icmp eq i64 %index.next, %n.vec + br i1 %10, label %middle.block, label %vector.body + +middle.block: ; preds = %vector.body + %cmp.n = icmp eq i64 %n.mod.vf, 0 + br i1 %cmp.n, label %for.cond.cleanup, label %for.body.preheader + +for.body.preheader: ; preds = %entry, %middle.block + %indvars.iv.ph = phi i64 [ 0, %entry ], [ %n.vec, %middle.block ] + br label %for.body + +for.cond.cleanup: ; preds = %for.body, %middle.block + ret void + +for.body: ; preds = %for.body.preheader, %for.body + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ %indvars.iv.ph, %for.body.preheader ] + %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv + %11 = load i32, i32* %arrayidx, align 4 + %add = add i32 %11, %x + store i32 %add, i32* %arrayidx, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %cmp.not = icmp eq i64 %indvars.iv.next, 1024 + br i1 %cmp.not, label %for.cond.cleanup, label %for.body +} + +declare <4 x i32> @llvm.vp.add.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32) + +define void @sink_splat_vp_add(i32* nocapture %a, i32 signext %x, <4 x i1> %m, i32 zeroext %vl) { +; CHECK-LABEL: sink_splat_vp_add: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: li a1, 1024 +; CHECK-NEXT: .LBB2_1: # %vector.body +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vle32.v v9, (a0) +; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma +; CHECK-NEXT: vadd.vv v9, v9, v8, v0.t +; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-NEXT: vse32.v v9, (a0) +; CHECK-NEXT: addi a1, a1, -4 +; CHECK-NEXT: addi a0, a0, 16 +; CHECK-NEXT: bnez a1, .LBB2_1 +; CHECK-NEXT: # %bb.2: # %for.cond.cleanup +; CHECK-NEXT: ret +entry: + %broadcast.splatinsert = insertelement <4 x i32> poison, i32 %x, i32 0 + %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds i32, i32* %a, i64 %index + %1 = bitcast i32* %0 to <4 x i32>* + %wide.load = load <4 x i32>, <4 x i32>* %1, align 4 + %2 = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %wide.load, <4 x i32> %broadcast.splat, <4 x i1> %m, i32 %vl) + %3 = bitcast i32* %0 to <4 x i32>* + store <4 x i32> %2, <4 x i32>* %3, align 4 + %index.next = add nuw i64 %index, 4 + %4 = icmp eq i64 %index.next, 1024 + br i1 %4, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body + ret void +} + +define void @sink_splat_fadd(float* nocapture %a, float %x) { +; CHECK-LABEL: sink_splat_fadd: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: li a1, 1024 +; CHECK-NEXT: .LBB3_1: # %vector.body +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vle32.v v9, (a0) +; CHECK-NEXT: vfadd.vv v9, v9, v8 +; CHECK-NEXT: vse32.v v9, (a0) +; CHECK-NEXT: addi a1, a1, -4 +; CHECK-NEXT: addi a0, a0, 16 +; CHECK-NEXT: bnez a1, .LBB3_1 +; CHECK-NEXT: # %bb.2: # %for.cond.cleanup +; CHECK-NEXT: ret +entry: + %broadcast.splatinsert = insertelement <4 x float> poison, float %x, i32 0 + %broadcast.splat = shufflevector <4 x float> %broadcast.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds float, float* %a, i64 %index + %1 = bitcast float* %0 to <4 x float>* + %wide.load = load <4 x float>, <4 x float>* %1, align 4 + %2 = fadd <4 x float> %wide.load, %broadcast.splat + %3 = bitcast float* %0 to <4 x float>* + store <4 x float> %2, <4 x float>* %3, align 4 + %index.next = add nuw i64 %index, 4 + %4 = icmp eq i64 %index.next, 1024 + br i1 %4, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body + ret void +} + +define void @sink_splat_fadd_scalable(float* nocapture %a, float %x) { +; CHECK-LABEL: sink_splat_fadd_scalable: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vlenb +; CHECK-NEXT: srli a3, a1, 2 +; CHECK-NEXT: li a2, 1024 +; CHECK-NEXT: bgeu a2, a3, .LBB4_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: li a2, 0 +; CHECK-NEXT: j .LBB4_5 +; CHECK-NEXT: .LBB4_2: # %vector.ph +; CHECK-NEXT: addi a2, a3, -1 +; CHECK-NEXT: andi a4, a2, 1024 +; CHECK-NEXT: xori a2, a4, 1024 +; CHECK-NEXT: vsetvli a5, zero, e32, m1, ta, ma +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: mv a5, a0 +; CHECK-NEXT: mv a6, a2 +; CHECK-NEXT: .LBB4_3: # %vector.body +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vl1re32.v v9, (a5) +; CHECK-NEXT: vfadd.vv v9, v9, v8 +; CHECK-NEXT: vs1r.v v9, (a5) +; CHECK-NEXT: sub a6, a6, a3 +; CHECK-NEXT: add a5, a5, a1 +; CHECK-NEXT: bnez a6, .LBB4_3 +; CHECK-NEXT: # %bb.4: # %middle.block +; CHECK-NEXT: beqz a4, .LBB4_7 +; CHECK-NEXT: .LBB4_5: # %for.body.preheader +; CHECK-NEXT: addi a1, a2, -1024 +; CHECK-NEXT: slli a2, a2, 2 +; CHECK-NEXT: add a0, a0, a2 +; CHECK-NEXT: .LBB4_6: # %for.body +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: flw fa5, 0(a0) +; CHECK-NEXT: fadd.s fa5, fa5, fa0 +; CHECK-NEXT: fsw fa5, 0(a0) +; CHECK-NEXT: addi a1, a1, 1 +; CHECK-NEXT: addi a0, a0, 4 +; CHECK-NEXT: bnez a1, .LBB4_6 +; CHECK-NEXT: .LBB4_7: # %for.cond.cleanup +; CHECK-NEXT: ret +entry: + %0 = call i64 @llvm.vscale.i64() + %1 = shl i64 %0, 1 + %min.iters.check = icmp ugt i64 %1, 1024 + br i1 %min.iters.check, label %for.body.preheader, label %vector.ph + +vector.ph: ; preds = %entry + %2 = call i64 @llvm.vscale.i64() + %3 = shl i64 %2, 1 + %n.mod.vf = urem i64 1024, %3 + %n.vec = sub nsw i64 1024, %n.mod.vf + %broadcast.splatinsert = insertelement <vscale x 2 x float> poison, float %x, i32 0 + %broadcast.splat = shufflevector <vscale x 2 x float> %broadcast.splatinsert, <vscale x 2 x float> poison, <vscale x 2 x i32> zeroinitializer + %4 = call i64 @llvm.vscale.i64() + %5 = shl i64 %4, 1 + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.bo... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/79015 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
