llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-mc @llvm/pr-subscribers-llvm-support Author: Wang Pengcheng (wangpc-pp) <details> <summary>Changes</summary> `A` extension has been split into two parts: Zaamo (Atomic Memory Operations) and Zalrsc (Load-Reserved/Store-Conditional). See also https://github.com/riscv/riscv-zaamo-zalrsc. This patch adds the MC support. --- Patch is 32.10 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/78970.diff 16 Files Affected: - (modified) clang/lib/Basic/Targets/RISCV.cpp (+1-1) - (modified) clang/test/Preprocessor/riscv-target-features.c (+18) - (modified) llvm/docs/RISCVUsage.rst (+2) - (modified) llvm/lib/Support/RISCVISAInfo.cpp (+2) - (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+25-1) - (modified) llvm/test/CodeGen/RISCV/attributes.ll (+8) - (modified) llvm/test/MC/RISCV/rv32i-invalid.s (+1-1) - (added) llvm/test/MC/RISCV/rv32zaamo-invalid.s (+11) - (added) llvm/test/MC/RISCV/rv32zaamo-valid.s (+122) - (added) llvm/test/MC/RISCV/rv32zalrsc-invalid.s (+7) - (added) llvm/test/MC/RISCV/rv32zalrsc-valid.s (+36) - (added) llvm/test/MC/RISCV/rv64zaamo-invalid.s (+11) - (added) llvm/test/MC/RISCV/rv64zaamo-valid.s (+157) - (added) llvm/test/MC/RISCV/rv64zalrsc-invalid.s (+7) - (added) llvm/test/MC/RISCV/rv64zalrsc-valid.s (+42) - (modified) llvm/unittests/Support/RISCVISAInfoTest.cpp (+2) ``````````diff diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index c71b2e9eeb6c172..9af9bdd1d74e9dd 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -175,7 +175,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__riscv_muldiv"); } - if (ISAInfo->hasExtension("a")) { + if (ISAInfo->hasExtension("a") || ISAInfo->hasExtension("zaamo")) { Builder.defineMacro("__riscv_atomic"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 5fde5ccdbeacfb0..38473d07004a574 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -141,7 +141,9 @@ // Experimental extensions +// CHECK-NOT: __riscv_zaamo {{.*$}} // CHECK-NOT: __riscv_zacas {{.*$}} +// CHECK-NOT: __riscv_zalrsc {{.*$}} // CHECK-NOT: __riscv_zcmop {{.*$}} // CHECK-NOT: __riscv_zfbfmin {{.*$}} // CHECK-NOT: __riscv_zicfilp {{.*$}} @@ -1307,6 +1309,14 @@ // CHECK-ZVKT-EXT: __riscv_zvkt 1000000{{$}} // Experimental extensions +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zaamo0p1 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zaamo0p1 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s +// CHECK-ZAAMO-EXT: __riscv_atomic 1 +// CHECK-ZAAMO-EXT: __riscv_zaamo 1000{{$}} // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32i_zacas1p0 -x c -E -dM %s \ @@ -1316,6 +1326,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s // CHECK-ZACAS-EXT: __riscv_zacas 1000000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zalrsc0p1 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zalrsc0p1 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s +// CHECK-ZALRSC-EXT: __riscv_zalrsc 1000{{$}} + // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32izfbfmin1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFBFMIN-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 6fdc945ad27078e..005e9f1d7324445 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -100,6 +100,8 @@ on support follow. ``V`` Supported ``Za128rs`` Supported (`See note <#riscv-profiles-extensions-note>`__) ``Za64rs`` Supported (`See note <#riscv-profiles-extensions-note>`__) + ``Zaamo`` Supported + ``Zalrsc`` Supported ``Zawrs`` Assembly Support ``Zba`` Supported ``Zbb`` Supported diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 3c02492e99f1db4..a5f00d14c94aa04 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -191,7 +191,9 @@ static const RISCVSupportedExtension SupportedExtensions[] = { // NOTE: This table should be sorted alphabetically by extension name. static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { + {"zaamo", {0, 1}}, {"zacas", {1, 0}}, + {"zalrsc", {0, 1}}, {"zcmop", {0, 2}}, diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index cbb096ba20ae67b..7c3a7a1937e2b2b 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -168,6 +168,18 @@ def FeatureStdExtZa64rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs", "true", def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs", "true", "'Za128rs' (Reservation Set Size of at Most 128 Bytes)">; +def FeatureStdExtZaamo + : SubtargetFeature<"experimental-zaamo", "HasStdExtZaamo", "true", + "'Zaamo' (Atomic Memory Operations)">; +def HasStdExtZaamo : Predicate<"Subtarget->hasStdExtZaamo()">, + AssemblerPredicate<(all_of FeatureStdExtZaamo), + "'Zaamo' (Atomic Memory Operations)">; +def HasStdExtAOrZaamo + : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZaamo()">, + AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZaamo), + "'A' (Atomic Instructions) or " + "'Zaamo' (Atomic Memory Operations)">; + def FeatureStdExtZacas : SubtargetFeature<"experimental-zacas", "HasStdExtZacas", "true", "'Zacas' (Atomic Compare-And-Swap Instructions)">; @@ -176,6 +188,18 @@ def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">, "'Zacas' (Atomic Compare-And-Swap Instructions)">; def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">; +def FeatureStdExtZalrsc + : SubtargetFeature<"experimental-zalrsc", "HasStdExtZalrsc", "true", + "'Zalrsc' (Load-Reserved/Store-Conditional)">; +def HasStdExtZalrsc : Predicate<"Subtarget->hasStdExtZalrsc()">, + AssemblerPredicate<(all_of FeatureStdExtZalrsc), + "'Zalrsc' (Load-Reserved/Store-Conditional)">; +def HasStdExtAOrZalrsc + : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc()">, + AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZalrsc), + "'A' (Atomic Instructions) or " + "'Zalrsc' (Load-Reserved/Store-Conditional)">; + def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true", "'Zawrs' (Wait on Reservation Set)">; def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">, @@ -1105,7 +1129,7 @@ def FeatureForcedAtomics : SubtargetFeature< "forced-atomics", "HasForcedAtomics", "true", "Assume that lock-free native-width atomics are available">; def HasAtomicLdSt - : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics()">; + : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc() || Subtarget->hasForcedAtomics()">; def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", "AllowTaggedGlobals", diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index b90bef7525379d1..e5be0267d134ea3 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -93,7 +93,9 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zaamo %s -o - | FileCheck --check-prefix=RV32ZAAMO %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zacas %s -o - | FileCheck --check-prefix=RV32ZACAS %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zalrsc %s -o - | FileCheck --check-prefix=RV32ZALRSC %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV32ZICFILP %s ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s @@ -195,7 +197,9 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zaamo %s -o - | FileCheck --check-prefix=RV64ZAAMO %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zacas %s -o - | FileCheck --check-prefix=RV64ZACAS %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zalrsc %s -o - | FileCheck --check-prefix=RV64ZALRSC %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV64ZICFILP %s ; CHECK: .attribute 4, 16 @@ -292,7 +296,9 @@ ; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0" ; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0" ; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" +; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo0p1" ; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0" +; RV32ZALRSC: .attribute 5, "rv32i2p1_zalrsc0p1" ; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p4" ; RV64M: .attribute 5, "rv64i2p1_m2p0" @@ -393,7 +399,9 @@ ; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0" ; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0" ; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" +; RV64ZAAMO: .attribute 5, "rv64i2p1_zaamo0p1" ; RV64ZACAS: .attribute 5, "rv64i2p1_a2p1_zacas1p0" +; RV64ZALRSC: .attribute 5, "rv64i2p1_zalrsc0p1" ; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp0p4" define i32 @addi(i32 %a) { diff --git a/llvm/test/MC/RISCV/rv32i-invalid.s b/llvm/test/MC/RISCV/rv32i-invalid.s index c5e0657b838094f..25a419cbefd4d00 100644 --- a/llvm/test/MC/RISCV/rv32i-invalid.s +++ b/llvm/test/MC/RISCV/rv32i-invalid.s @@ -170,7 +170,7 @@ xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction # Instruction not in the base ISA div a4, ra, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'M' (Integer Multiplication and Division){{$}} -amomaxu.w s5, s4, (s3) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'A' (Atomic Instructions){{$}} +amomaxu.w s5, s4, (s3) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'A' (Atomic Instructions) or 'Zaamo' (Atomic Memory Operations){{$}} fadd.s ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}} fadd.h ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}} fadd.s a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfinx' (Float in Integer){{$}} diff --git a/llvm/test/MC/RISCV/rv32zaamo-invalid.s b/llvm/test/MC/RISCV/rv32zaamo-invalid.s new file mode 100644 index 000000000000000..f5974828d90c4ab --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zaamo-invalid.s @@ -0,0 +1,11 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zaamo < %s 2>&1 | FileCheck %s + +# Final operand must have parentheses +amoswap.w a1, a2, a3 # CHECK: :[[@LINE]]:19: error: expected '(' or optional integer offset +amomin.w a1, a2, 1 # CHECK: :[[@LINE]]:20: error: expected '(' after optional integer offset +amomin.w a1, a2, 1(a3) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0 + +# Only .aq, .rl, and .aqrl suffixes are valid +amoxor.w.rlqa a2, a3, (a4) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic +amoor.w.aq.rl a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic +amoor.w. a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic diff --git a/llvm/test/MC/RISCV/rv32zaamo-valid.s b/llvm/test/MC/RISCV/rv32zaamo-valid.s new file mode 100644 index 000000000000000..18b31cd0083363c --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zaamo-valid.s @@ -0,0 +1,122 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zaamo -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zaamo -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zaamo < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zaamo -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zaamo < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zaamo -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: amoswap.w a4, ra, (s0) +# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x08] +amoswap.w a4, ra, (s0) +# CHECK-ASM-AND-OBJ: amoadd.w a1, a2, (a3) +# CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x00] +amoadd.w a1, a2, (a3) +# CHECK-ASM-AND-OBJ: amoxor.w a2, a3, (a4) +# CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x20] +amoxor.w a2, a3, (a4) +# CHECK-ASM-AND-OBJ: amoand.w a3, a4, (a5) +# CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x60] +amoand.w a3, a4, (a5) +# CHECK-ASM-AND-OBJ: amoor.w a4, a5, (a6) +# CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x40] +amoor.w a4, a5, (a6) +# CHECK-ASM-AND-OBJ: amomin.w a5, a6, (a7) +# CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x81] +amomin.w a5, a6, (a7) +# CHECK-ASM-AND-OBJ: amomax.w s7, s6, (s5) +# CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa1] +amomax.w s7, s6, (s5) +# CHECK-ASM-AND-OBJ: amominu.w s6, s5, (s4) +# CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc1] +amominu.w s6, s5, (s4) +# CHECK-ASM-AND-OBJ: amomaxu.w s5, s4, (s3) +# CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe1] +amomaxu.w s5, s4, (s3) + +# CHECK-ASM-AND-OBJ: amoswap.w.aq a4, ra, (s0) +# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x0c] +amoswap.w.aq a4, ra, (s0) +# CHECK-ASM-AND-OBJ: amoadd.w.aq a1, a2, (a3) +# CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x04] +amoadd.w.aq a1, a2, (a3) +# CHECK-ASM-AND-OBJ: amoxor.w.aq a2, a3, (a4) +# CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x24] +amoxor.w.aq a2, a3, (a4) +# CHECK-ASM-AND-OBJ: amoand.w.aq a3, a4, (a5) +# CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x64] +amoand.w.aq a3, a4, (a5) +# CHECK-ASM-AND-OBJ: amoor.w.aq a4, a5, (a6) +# CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x44] +amoor.w.aq a4, a5, (a6) +# CHECK-ASM-AND-OBJ: amomin.w.aq a5, a6, (a7) +# CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x85] +amomin.w.aq a5, a6, (a7) +# CHECK-ASM-AND-OBJ: amomax.w.aq s7, s6, (s5) +# CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa5] +amomax.w.aq s7, s6, (s5) +# CHECK-ASM-AND-OBJ: amominu.w.aq s6, s5, (s4) +# CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc5] +amominu.w.aq s6, s5, (s4) +# CHECK-ASM-AND-OBJ: amomaxu.w.aq s5, s4, (s3) +# CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe5] +amomaxu.w.aq s5, s4, (s3) + +# CHECK-ASM-AND-OBJ: amoswap.w.rl a4, ra, (s0) +# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x0a] +amoswap.w.rl a4, ra, (s0) +# CHECK-ASM-AND-OBJ: amoadd.w.rl a1, a2, (a3) +# CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x02] +amoadd.w.rl a1, a2, (a3) +# CHECK-ASM-AND-OBJ: amoxor.w.rl a2, a3, (a4) +# CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x22] +amoxor.w.rl a2, a3, (a4) +# CHECK-ASM-AND-OBJ: amoand.w.rl a3, a4, (a5) +# CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x62] +amoand.w.rl a3, a4, (a5) +# CHECK-ASM-AND-OBJ: amoor.w.rl a4, a5, (a6) +# CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x42] +amoor.w.rl a4, a5, (a6) +# CHECK-ASM-AND-OBJ: amomin.w.rl a5, a6, (a7) +# CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x83] +amomin.w.rl a5, a6, (a7) +# CHECK-ASM-AND-OBJ: amomax.w.rl s7, s6, (s5) +# CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa3] +amomax.w.rl s7, s6, (s5) +# CHECK-ASM-AND-OBJ: amominu.w.rl s6, s5, (s4) +# CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc3] +amominu.w.rl s6, s5, (s4) +# CHECK-ASM-AND-OBJ: amomaxu.w.rl s5, s4, (s3) +# CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe3] +amomaxu.w.rl s5, s4, (s3) + +# CHECK-ASM-AND-OBJ: amoswap.w.aqrl a4, ra, (s0) +# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x0e] +amoswap.w.aqrl a4, ra, (s0) +# CHECK-ASM-AND-OBJ: amoadd.w.aqrl a1, a2, (a3) +# CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x06] +amoadd.w.aqrl a1, a2, (a3) +# CHECK-ASM-AND-OBJ: amoxor.w.aqrl a2, a3, (a4) +# CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x26] +amoxor.w.aqrl a2, a3, (a4) +# CHECK-ASM-AND-OBJ: amoand.w.aqrl a3, a4, (a5) +# CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x66] +amoand.w.aqrl a3, a4, (a5) +# CHECK-ASM-AND-OBJ: amoor.w.aqrl a4, a5, (a6) +# CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x46] +amoor.w.aqrl a4, a5, (a6) +# CHECK-ASM-AND-OBJ: amomin.w.aqrl a5, a6, (a7) +# CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x87] +amomin.w.aqrl a5, a6, (a7) +# CHECK-ASM-AND-OBJ: amomax.w.aqrl s7, s6, (s5) +# CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa7] +amomax.w.aqrl s7, s6, (s5) +# CHECK-ASM-AND-OBJ: amominu.w.aqrl s6, s5, (s4) +# CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc7] +amominu.w.aqrl s6, s5, (s4) +# CHECK-ASM-AND-OBJ: amomaxu.w.aqrl s5, s4, (s3) +# CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe7] +amomaxu.w.aqrl s5, s4, (s3) diff --git a/llvm/test/MC/RISCV/rv32zalrsc-invalid.s b/llvm/test/MC/RISCV/rv32zalrsc-invalid.s new file mode 100644 index 000000000000000..01e5a19a335aff8 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zalrsc-invalid.s @@ -0,0 +1,7 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zalrsc < %s 2>&1 | FileCheck %s + +# Final operand must have parentheses +lr.w a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset + +# lr only takes two operands +lr.w s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv32zalrsc-valid.s b/llvm/test/MC/RISCV/rv32zalrsc-valid.s new file mode 100644 index 000000000000000..08c84f889792906 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zalrsc-valid.s @@ -0,0 +1,36 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zalrsc -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zalrsc -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zalrsc < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zalrsc -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zalrsc < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zalrsc -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: lr.w t0, (t1) +# CHECK-ASM: encoding: [0xaf,0x22,0x03,0x10] +lr.w t0, (t1) +# CHECK-ASM-AND-OBJ: lr.w.aq t1, (t2) +# CHECK-ASM: encoding: [0x2f,0xa3,0x03,0x14] +lr.w.aq t1, (t2) +# CHECK-ASM-AND-OBJ: lr.w.rl t2, (t3) +# CHECK-ASM: encoding: [0xaf,0x23,0x0e,0x12] +lr.w.rl t2, (t3) +# CHECK-ASM-AND-OBJ: lr.w.aqrl t3, (t4) +# CHECK-ASM: encoding: [0x2f,0xae,0x0e,0x16] +lr.w.aqrl t3, (t4) + +# CHECK-ASM-AND-OBJ: sc.w t6, t5, (t4) +# CHECK-ASM: encoding: [0xaf,0xaf,0xee,0x19] +sc.w t6, t5, (t4) +# CHECK-ASM-AND-OBJ: sc.w.aq t5, t4, (t3) +# CHECK-ASM: encoding: [0x2f,0x2f,0xde,0x1d] +sc.w.aq t5, t4, (t3) +# CHECK-ASM-AND-OBJ: sc.w.rl t4, t3, (t2) +# CHECK-ASM: encoding: [0xaf,0xae,0xc3,0x1b] +sc.w.rl t4, t3, (t2) +# CHECK-ASM-AND-OBJ: sc.w.aqrl t3, t2, (t1) +# CHECK-ASM: encoding: [0x2f,0x2e,0x73,0x1e] +sc.w.aqrl t3, t2, (t1) diff --git a/llvm/test/MC/RISCV/rv64zaamo-invalid.s b/llvm/test/MC/RISCV/rv64zaamo-invalid.s new file mode 100644 index 000000000000000..d196de83034261b --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zaamo-invalid.s @@ -0,0 +1,11 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zaamo < %s 2>&1 | FileCheck %s + +# Final operand must have parentheses +amoswap.d a1, a2, a3 # CHECK: :[[@LINE]]:19: error: expected '(' or optional integer offset +amomin.d a1, a2, 1 # CHECK: :[[@LINE]]:20: error: expected '(' after optional integer offset +amomin.d a1, a2, 1(a3) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0 + +# Only .aq, .rl, and .aqrl suffixes are valid +amoxor.d.rlqa a2, a3, (a4) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic +amoor.d.aq.rl a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic +amoor.d. a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic diff --git a/llvm/test/MC/... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/78970 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
