https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76893
>From c4f7441b2809dfbb6ed4b6d97d581e3d736819fe Mon Sep 17 00:00:00 2001 From: wangpc <wangpengcheng...@bytedance.com> Date: Thu, 4 Jan 2024 13:05:53 +0800 Subject: [PATCH] [RISCV] Add B extension It seems that we have `B` extension again: https://github.com/riscv/riscv-b According to the spec, `B` extension represents the collection of the `Zba`, `Zbb`, `Zbs` extensions. Though it hasn't been ratified, I set its version to `1.0`. --- clang/test/Driver/riscv-arch.c | 5 ----- clang/test/Preprocessor/riscv-target-features.c | 12 ++++++++++++ llvm/docs/RISCVUsage.rst | 1 + llvm/lib/Support/RISCVISAInfo.cpp | 5 ++++- llvm/lib/Target/RISCV/RISCVFeatures.td | 8 ++++++++ llvm/test/CodeGen/RISCV/attributes.ll | 4 ++++ llvm/unittests/Support/RISCVISAInfoTest.cpp | 6 ++---- 7 files changed, 31 insertions(+), 10 deletions(-) diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c index 0ac81ea982f1b61..7c9f880c74035ba 100644 --- a/clang/test/Driver/riscv-arch.c +++ b/clang/test/Driver/riscv-arch.c @@ -233,11 +233,6 @@ // RV32-STD: error: invalid arch name 'rv32imqc', // RV32-STD: unsupported standard user-level extension 'q' -// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \ -// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s -// RV32-B: error: invalid arch name 'rv32ib', -// RV32-B: unsupported standard user-level extension 'b' - // RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s // RV32X: error: invalid arch name 'rv32xabc', diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 8dc02f7efefbd6f..6acd7b1f2d6d6ad 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -7,6 +7,7 @@ // CHECK-NOT: __riscv_64e {{.*$}} // CHECK-NOT: __riscv_a {{.*$}} // CHECK-NOT: __riscv_atomic +// CHECK-NOT: __riscv_b {{.*$}} // CHECK-NOT: __riscv_c {{.*$}} // CHECK-NOT: __riscv_compressed {{.*$}} // CHECK-NOT: __riscv_d {{.*$}} @@ -159,6 +160,17 @@ // CHECK-A-EXT: __riscv_a 2001000{{$}} // CHECK-A-EXT: __riscv_atomic 1 +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32ib -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64ib -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s +// CHECK-B-EXT: __riscv_b 1000000{{$}} +// CHECK-B-EXT: __riscv_zba 1000000{{$}} +// CHECK-B-EXT: __riscv_zbb 1000000{{$}} +// CHECK-B-EXT: __riscv_zbs 1000000{{$}} + // RUN: %clang --target=riscv32-unknown-linux-gnu \ // RUN: -march=rv32ic -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index fc4d97b13437153..bfdceb81ce2dc76 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -85,6 +85,7 @@ on support follow. Extension Status =============== ========================================================= ``A`` Supported + ``B`` Supported ``C`` Supported ``D`` Supported ``F`` Supported diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 8c9eb1bddb3cb52..1f194851d0681e4 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -46,6 +46,7 @@ static const char *RISCVGImplications[] = { // NOTE: This table should be sorted alphabetically by extension name. static const RISCVSupportedExtension SupportedExtensions[] = { {"a", {2, 1}}, + {"b", {1, 0}}, {"c", {2, 0}}, {"d", {2, 2}}, {"e", {2, 0}}, @@ -848,7 +849,7 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, } // The order is OK, then push it into features. - // Currently LLVM supports only "mafdcvh". + // Currently LLVM supports only "mafdcbvh". if (!isSupportedExtension(StringRef(&C, 1))) { if (IgnoreUnknown) { GoToNextExt(I, ConsumeLength, Exts.end()); @@ -998,6 +999,7 @@ Error RISCVISAInfo::checkDependency() { return Error::success(); } +static const char *ImpliedExtsB[] = {"zba", "zbb", "zbs"}; static const char *ImpliedExtsD[] = {"f"}; static const char *ImpliedExtsF[] = {"zicsr"}; static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"}; @@ -1072,6 +1074,7 @@ struct ImpliedExtsEntry { // Note: The table needs to be sorted by name. static constexpr ImpliedExtsEntry ImpliedExts[] = { + {{"b"}, {ImpliedExtsB}}, {{"d"}, {ImpliedExtsD}}, {{"f"}, {ImpliedExtsF}}, {{"v"}, {ImpliedExtsV}}, diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 72780937dd88704..cbde0e9b3a0e1b8 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -225,6 +225,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">, AssemblerPredicate<(all_of FeatureStdExtZbs), "'Zbs' (Single-Bit Instructions)">; +def FeatureStdExtB + : SubtargetFeature<"b", "HasStdExtB", "true", + "'B' (the collection of the Zba, Zbb, Zbs extensions)", + [FeatureStdExtZba, FeatureStdExtZbb, FeatureStdExtZbs]>; +def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">, + AssemblerPredicate<(all_of FeatureStdExtB), + "'B' (the collection of the Zba, Zbb, Zbs extensions)">; + def FeatureStdExtZbkb : SubtargetFeature<"zbkb", "HasStdExtZbkb", "true", "'Zbkb' (Bitmanip instructions for Cryptography)">; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 3e55e0fb4e6861e..e5609d5e84d01df 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -5,6 +5,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV32ZMMUL %s ; RUN: llc -mtriple=riscv32 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV32MZMMUL %s ; RUN: llc -mtriple=riscv32 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV32A %s +; RUN: llc -mtriple=riscv32 -mattr=+b %s -o - | FileCheck --check-prefixes=CHECK,RV32B %s ; RUN: llc -mtriple=riscv32 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV32F %s ; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV32D %s ; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefixes=CHECK,RV32C %s @@ -100,6 +101,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64ZMMUL %s ; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64MZMMUL %s ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV64A %s +; RUN: llc -mtriple=riscv64 -mattr=+b %s -o - | FileCheck --check-prefixes=CHECK,RV64B %s ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV64F %s ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV64D %s ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefixes=CHECK,RV64C %s @@ -202,6 +204,7 @@ ; RV32ZMMUL: .attribute 5, "rv32i2p1_zmmul1p0" ; RV32MZMMUL: .attribute 5, "rv32i2p1_m2p0_zmmul1p0" ; RV32A: .attribute 5, "rv32i2p1_a2p1" +; RV32B: .attribute 5, "rv32i2p1_b1p0_zba1p0_zbb1p0_zbs1p0" ; RV32F: .attribute 5, "rv32i2p1_f2p2_zicsr2p0" ; RV32D: .attribute 5, "rv32i2p1_f2p2_d2p2_zicsr2p0" ; RV32C: .attribute 5, "rv32i2p1_c2p0" @@ -296,6 +299,7 @@ ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0" ; RV64MZMMUL: .attribute 5, "rv64i2p1_m2p0_zmmul1p0" ; RV64A: .attribute 5, "rv64i2p1_a2p1" +; RV64B: .attribute 5, "rv64i2p1_b1p0_zba1p0_zbb1p0_zbs1p0" ; RV64F: .attribute 5, "rv64i2p1_f2p2_zicsr2p0" ; RV64D: .attribute 5, "rv64i2p1_f2p2_d2p2_zicsr2p0" ; RV64C: .attribute 5, "rv64i2p1_c2p0" diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp index 0b8bbc7c9027ec8..01aad13c68a0645 100644 --- a/llvm/unittests/Support/RISCVISAInfoTest.cpp +++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp @@ -222,8 +222,6 @@ TEST(ParseArchString, RequiresCanonicalOrderForSingleLetterExtensions) { } TEST(ParseArchString, RejectsUnrecognizedExtensionNamesByDefault) { - EXPECT_EQ(toString(RISCVISAInfo::parseArchString("rv64ib", true).takeError()), - "unsupported standard user-level extension 'b'"); EXPECT_EQ( toString( RISCVISAInfo::parseArchString("rv32i_zmadeup", true).takeError()), @@ -239,8 +237,7 @@ TEST(ParseArchString, RejectsUnrecognizedExtensionNamesByDefault) { } TEST(ParseArchString, IgnoresUnrecognizedExtensionNamesWithIgnoreUnknown) { - for (StringRef Input : {"rv32ib", "rv32i_zmadeup", - "rv64i_smadeup", "rv64i_xmadeup"}) { + for (StringRef Input : {"rv32i_zmadeup", "rv64i_smadeup", "rv64i_xmadeup"}) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true, false, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); RISCVISAInfo &Info = **MaybeISAInfo; @@ -673,6 +670,7 @@ R"(All available -march extensions for RISC-V f 2.2 d 2.2 c 2.0 + b 1.0 v 1.0 h 1.0 zic64b 1.0 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
