================
@@ -57046,17 +57046,17 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
// in the normal allocation?
case 'k':
if (Subtarget.hasAVX512()) {
- if (VT == MVT::i1)
+ if (VT == MVT::v1i1 || VT == MVT::i1)
return std::make_pair(0U, &X86::VK1RegClass);
- if (VT == MVT::i8)
+ if (VT == MVT::v8i1 || VT == MVT::i8)
return std::make_pair(0U, &X86::VK8RegClass);
- if (VT == MVT::i16)
+ if (VT == MVT::v16i1 || VT == MVT::i16)
return std::make_pair(0U, &X86::VK16RegClass);
}
if (Subtarget.hasBWI()) {
- if (VT == MVT::i32)
+ if (VT == MVT::v32i1 || VT == MVT::i32)
return std::make_pair(0U, &X86::VK32RegClass);
- if (VT == MVT::i64)
+ if (VT == MVT::v64i1 || VT == MVT::i64)
return std::make_pair(0U, &X86::VK64RegClass);
----------------
KanRobert wrote:
i1, i8, i16 is kept for what? backward compatibility of IR?
https://github.com/llvm/llvm-project/pull/77733
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