Thorsten =?utf-8?q?Schütt?= <[email protected]>,
Thorsten =?utf-8?q?Schütt?= <[email protected]>,
Thorsten =?utf-8?q?Schütt?= <[email protected]>
Message-ID:
In-Reply-To: <llvm.org/llvm/llvm-project/pull/[email protected]>
================
@@ -6548,6 +6534,54 @@ bool CombinerHelper::tryFoldBoolSelectToLogic(GSelect
*Select,
return false;
}
+bool CombinerHelper::tryFoldSelectOfBinOps(GSelect *Select,
+ BuildFnTy &MatchInfo) {
+ Register DstReg = Select->getReg(0);
+ Register Cond = Select->getCondReg();
+ Register False = Select->getFalseReg();
+ Register True = Select->getTrueReg();
+ LLT DstTy = MRI.getType(DstReg);
+
+ GBinOp *LHS = getOpcodeDef<GBinOp>(True, MRI);
+ GBinOp *RHS = getOpcodeDef<GBinOp>(False, MRI);
+
+ // We need two binops of the same kind on the true/false registers.
+ if (!LHS || !RHS || LHS->getOpcode() != RHS->getOpcode())
+ return false;
+
+ // Note that there are no constraints on CondTy.
+ unsigned Flags = (LHS->getFlags() & RHS->getFlags()) | Select->getFlags();
----------------
arsenm wrote:
I would have split this by matching the DAG behavior in the initial commit but
doesn't really matter. I *think* this is OK but would be nice to have alive
verify
https://github.com/llvm/llvm-project/pull/76763
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