jyknight wrote: > This sounds extremely unsound
It is completely unsound. The constraints that approximately every architecture has on LL/SC loops make it unsound to ever generate isolated LL and SC instructions at the IR level, as we are currently doing on AArch64, ARM, and Hexagon. We already added the infrastructure to do this properly, and used it for RISCV, and it's now also being used on Loongarch. ARM/AArch64 should be updated to match. See discussion in https://lists.llvm.org/pipermail/llvm-dev/2018-June/123993.html https://github.com/llvm/llvm-project/pull/74588 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
